Attempting my first Layout to Allegro translation, and am getting an error :Originally posted in cdnusers.org by dschaefer
ERROR (Layout To PCBEditor), Padstack 'V_TP_SM' is malformed on layer 1
The Layout padstack is a Via being used as a Testpoint on the Bottom surface only, so it is defined as having features on Layout Bottom and Bottom Soldermask only, all other layers are undefined.
Anyone run into a similar problem? The error logs that are created include only the information I've listed above.