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 Back Annotate problems between Capture (10.5) and Allegro PCB design (15.2) 

Last post Mon, Oct 30 2006 3:32 PM by archive. 3 replies.
Started by archive 30 Oct 2006 03:32 PM. Topic has 3 replies and 897 views
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  • Mon, Oct 30 2006 3:32 PM

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    Back Annotate problems between Capture (10.5) and Allegro PCB design (15.2) Reply

    Hey guys, my first post and it is a long one. Let's see if I can explain me correctly.

    We are having problems with the Back annotation process between Allegro 15.2 and Capture 10.2. The process works something like this:

    - We update our schematic and generate a netlist
    - Send this netlist to our PCB Engineer, so he can update his PCB file.
    - He then updates/changes nets with new rules, constrains, propagation delay values, etc. then sends us the updated board file back for syncing
    - Once we receive the file, we do the back annotation process in Capture (Tools-Back Annotate-Allegro) to keep the entire design in-sync
    - After going through the automated process, the SWP file generated is "blank" (file size ~1k)
    - We check if the databases are synced manually, and they do seem to be in order. What puzzles us is the fact that certain properties do not appear in the Schematic

    Any comments? Solutions perhaps?


    Originally posted in cdnusers.org by waldo15
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  • Tue, Oct 31 2006 9:07 AM

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    RE: Back Annotate problems between Capture (10.5) and Allegro PCB design (15.2) Reply

    Well I don't know where to start here but I'll hit the first thing in that allegro 15.2 goes with capture 10.2 and 10.3, As  Allegro 15.5 and 15.5.1 go with Capture 10.5 It appears you are trying to mix the releases not sure this has anything to do with the problem but its definitely not the recommended procedure. I have had these problems backannotating before and I always keep the release strams from Cadence in tact. What I have seen cause these problems in the past are the following.

    1) Schematic design name has been changed since the netlist has been read in to allegro
    2) The schematic had electrical rules like rel prop delay in it and came from an earlier capture release such as 9.2.3  where there was no rule syntax checking and the syntax was bad therefore capture in its infinite wisdom blanks out the rule and passes that blank to allegro.
    3) Constraint Manager was used in allegro to add delete or change rules.


    Originally posted in cdnusers.org by CTMusetti
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  • Tue, Oct 31 2006 9:31 AM

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    RE: Back Annotate problems between Capture (10.5) and Allegro PCB design (15.2) Reply



    1) Schematic design name has been changed since the netlist has been read in to allegro
    2) The schematic had electrical rules like rel prop delay in it and came from an earlier capture release such as 9.2.3  where there was no rule syntax checking and the syntax was bad therefore capture in its infinite wisdom blanks out the rule and passes that blank to allegro.
    3) Constraint Manager was used in allegro to add delete or change rules.




    Thanks for the prompt response:

    1) Indeed we change the schematic name every time we get an update. We'll test this without name changes
    2) We have not generated (as far as I know) rules in Capture 9.X versions, we have only used 10.X
    3) Yes, we use Constrain Manager. Can we use something else without getting this issue? Or if we cannot change the use of constrain manager, any suggestions on how to fix it?

    Best regards,

    Jorge Martinez
    HW engineer


    Originally posted in cdnusers.org by waldo15
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  • Wed, Nov 1 2006 8:10 AM

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    RE: Back Annotate problems between Capture (10.5) and Allegro PCB design (15.2) Reply

    Jorge,

        I use CM all the time, to me it is unacceptable not to be able to use it. You can go and edit the properties through the property editor but it is much easier and faster in CM, and furthurmore there are properties which you can not add now to nets in the property editor now in REL 15.2 and beyond such as RELATIVE_PROP_DELAY.  The solution here is for us user to continue to beat on Cadence to add the CM to ORCAD as their position on not supporting CM through ORCAD is ludicrous based on what I just mentioned above, and obviously the complete flow with exchanging rules is broken with out it. I have opened numerous SR's on problems revloving around this central issue, and have gotten work arounds but hvae not been succesful in getting Cadence to recognize that there is a need for CM support on ORCAD. The way I have been succesful in transferring rules enter or changed through CM back to ORCAD is to delete all the net properties in the ORCAD schematic. then run the back annotation. You still need to be careful with this as CM supports things that ORCAD doesn't such as the RELATIVE_PROP_DELAY in CM supports multiple match groups ORCAD only has support for one.

        If you have changed the name on the schematic it is definitely you problem. Here is an excerpt of an email frm cadence support  from an SR iI had on a similar problem. Read below:

    Hello Carl,

     

    This issue has been fixed in our next release 15.7 which is due to be released in July this year.

    A Message is displayed at the time of Back-Annotation if the design name is changed after creating the board

     

    I hope this helps.

    With Best Regards,
    Prabhjot


    From: Musetti, Carl [mailto:cmusetti@silverstorm.com]
    Sent: Tuesday, June 13, 2006 8:17 PM
    To: Prabhjot Kaur
    Subject: RE: Back Annotation creates DRC's

     

    Thanks!

     


    From: Prabhjot Kaur [mailto:prabhjot@cadence.com]
    Sent: Tuesday, June 13, 2006 8:45 AM
    To: Musetti, Carl
    Subject: RE: Back Annotation creates DRC's

     

    Hello Carl,

     

    As per your feedback, I have filed a PCR to address the issue of back annotation failing when design name changes.

    The PCR addressing the change is 905469 (Title: 'user warned when Design name changes are made').

     

     I hope this helps.

    With Best Regards,
    Prabhjot


    From: Musetti, Carl [mailto:cmusetti@silverstorm.com]
    Sent: Thursday, June 08, 2006 8:29 PM
    To: Prabhjot Kaur
    Subject: RE: Back Annotation creates DRC's

     

    Well the only thing that is disturbing is the lack of error checking / prevention of bad data getting into allegro through the import logic. I think this should be better handled by allegro. As the bad rule set cam in some time ago when we were on 10.3 and rules were getting broken when upreving from 10.2 and below !0.3 was a bda release 10.5 seems to be much more robust!  I would also like to see Cadence make an effort in having tools for the ORCAD allegro flow to manage the annotation backannotation processes and the design reuse processes. A good example of the lack of it is here

     

    http://www.cdnusers.org/Forums/tabid/52/view/topics/forumid/5/Default.aspx

     

    see

     

    Allegro - OrCAD Reuse module Procedure Problems

     

    But you can close this ISR I guess all I’m try to say is its all too easy too shoot yourself in the foot with the flow.

     

    Thanks

    Carl




       


    Originally posted in cdnusers.org by CTMusetti
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Started by archive at 30 Oct 2006 03:32 PM. Topic has 3 replies.