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 Concept HDL Error 

Last post Tue, Jul 11 2006 8:47 PM by archive. 7 replies.
Started by archive 11 Jul 2006 08:47 PM. Topic has 7 replies and 1898 views
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  • Tue, Jul 11 2006 8:47 PM

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    Concept HDL Error Reply

    Hi guys! Al here again. I encountered an error while saving my schematic entry. The error reads Place holder property needs value set.

    And when I am exporting the physical definition I encounter this error:

    #1 ERROR(304): Cannot find a .sir file for '@pcb_lib.xc3s200pq208(entity)'. ~

    Verify you have saved all changes to cell 'xc3s200pq208'.

    In addition, verify the correct library for cell 'xc3s200pq208' has be~

    en specified in the liblist of all cfg_package/expand.cfg files used during ex~

    pansion of this design.

    When binding to '@pcb_lib.xc3s200pq208(chips)', the port definition is~

    determined using the 'entity' view.

    1 errors detected

    Thanks for the help. Ü

    - Al


    Originally posted in cdnusers.org by acbalbason
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  • Wed, Jul 12 2006 5:19 AM

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    RE: Concept HDL Error Reply

    Hi Al,

    There can be a couple causes for this error. I found this Solution posted on SourceLink. For search criteria, I
    entered "ERROR 304 : Cannot find a .sir file for". Please see this SourceLink URL - http://sourcelink.cadence.com/docs/db/kdb/2004/June/11140772.html

    Here's the content of the Solution# 11140772:
    *Error_Message:


    #1 ERROR(304): Cannot find a .sir file for '@test_lib.abc(sch_1)'. Ve~
    rify you have saved all changes to cell 'capacitor'.
    In addition, verify the correct library for cell 'abc' has been ~
    specified in the liblist of all cfg_package/expand.cfg files used during expan~
    sion of this design.

    *Problem:


    I am trying to run Export physical on my design and I am getting the Error 304. How
    do I resolve this error?

    *Solution:


    This reason why this error occurs is because the entity view of the component for
    which this error is being reported does not have the vlog004u.sir file. In order
    to generate the files for the components in question, please follow these steps:

    a) Locate all the components (one-by-one) reported by this Error #304 by viewing
    the pxl.log file by selecting any particular instance for that component in the
    schematic.
    b) In ConceptHDL, double-click on that component instance to view the symbol.
    c) Now do a File->Save in ConceptHDL in order to save the symbol. This will
    regenerate the entity view and will generate the vlog004u.sir file as well.
    d) Repeat the steps a - c for all the other components in error.
    e) Save the design and re-run Export Physical.

    Jerry


    Originally posted in cdnusers.org by geraldg
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  • Wed, Jul 12 2006 8:25 PM

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    RE: Concept HDL Error Reply

    Hi Jerry,

    It worked actually. Thanks! Now I have a new problem. I need to generate the footprint of the schematic symbol. I got my symbol from http://www.accelerated-designs.com. It is a PQ208 Package of Xilinx FPGA XC3S200. It has a CSV file (.ctx file extension). The guy from ADI says i need a footprint generator to generate the footprint. You know of any Allegro product which does this?

    Thanks,

    Al


    Originally posted in cdnusers.org by acbalbason
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  • Wed, Jul 12 2006 8:25 PM

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    RE: Concept HDL Error Reply

    Hi Jerry,

    It worked actually. Thanks! Now I have a new problem. I need to generate the footprint of the schematic symbol. I got my symbol from http://www.accelerated-designs.com. It is a PQ208 Package of Xilinx FPGA XC3S200. It has a CSV file (.ctx file extension). The guy from ADI says i need a footprint generator to generate the footprint. You know of any Allegro product which does this?

    Thanks,

    Al


    Originally posted in cdnusers.org by acbalbason
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  • Wed, Jul 12 2006 8:25 PM

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    RE: Concept HDL Error Reply

    Hi Jerry,

    It worked actually. Thanks! Now I have a new problem. I need to generate the footprint of the schematic symbol. I got my symbol from http://www.accelerated-designs.com. It is a PQ208 Package of Xilinx FPGA XC3S200. It has a CSV file (.ctx file extension). The guy from ADI says i need a footprint generator to generate the footprint. You know of any Allegro product which does this?

    Thanks,

    Al


    Originally posted in cdnusers.org by acbalbason
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  • Wed, Jul 12 2006 8:39 PM

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    RE: Concept HDL Error Reply

    Hi Al,

    Glad the solution above resolved your problem. I'm a front-end (ConceptHDL/PCB Librarian/etc.) type person and don't have much experience with footprint/pad
    building.

    From what you've described, you have a .CSV file. While this Excel format can be
    imported into PCB Librarian to generate the schematic symbol and chips.prt
    files, I don't know of a method to automatically generate the footprint from
    a .CSV file. Of course, you would use Allegro PCB Editor to build the padstacks
    and footprint - but this is a manual process - easy, but manual.

    You may try posting another message with the subject line of how to automatically
    generate an Allegro footprint from a Xilinx .CSV file.

    Good luck,

    Jerry


    Originally posted in cdnusers.org by geraldg
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  • Thu, Jul 13 2006 5:55 AM

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    RE: Concept HDL Error Reply

    I suspect that what you have in the ctx file is a proprietary format used by the Accelerated Design Ultra Librarian tool. They are in the business of selling library development tools and libraries. I am reasonably confident there is no direct interface to import a ctx file directly into Allegro to create a footprint. You would need their Ultra Librarian tool.


    Originally posted in cdnusers.org by cdavies
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  • Thu, Jul 13 2006 7:56 AM

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    RE: Concept HDL Error Reply

    Thanks Charlie! I actually downloaded their Librarian. I am thinking of installing PCB Librarian Expert by Allegro before I read your post. But the guy from CADPLEX says that it should work.

    It should. A ctx file is a csv file or comma seperated value file. You may need to bring it up in Excel and move the columns around to whatever Cadence PCB Librarian Expert expects.
    Regards
    Mike Bitzko

    acbalbason@aim.com wrote:

    Hi Mike, It actually worked! Thanks! Can you suggest any Cadence product that generates footprints? I saw a tutorial and PCB Librarian Expert actually creates footprints but it uses .csv filename extensions. Will it also work for .ctx files? - Al

    Any comments? Thanks for the help! Ü

    - Al


    Originally posted in cdnusers.org by acbalbason
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Started by archive at 11 Jul 2006 08:47 PM. Topic has 7 replies.