I couldn't agree with you more. I have preached
those same words to my management but they are so tigh that when you
hold them upside down their change doesn't fall out of their pockets.
Apperently they have more faith in me than they have in tools like that
and don't see the need as I have not yet given them a bad board to work
with. But I feel I am living on borrowed time here with the
technologies I am getting into and given the limits of Allegro DRC
system, which really in all is the best I have worked with as far as
PCB design goes.
I created the buried resistors as component which came from the ORCAD
schematic the pins are modeled as padstacks on the specific layers they
are designed on. There is a second artwork layer is generated for 2nd
etch process for the resistive material that is model as a shape on the
package geometry layer. I can't see any reference to that in the IPC
Anyway the problem turns out to be a netlist interpreatation problem on
Valors part but maybe someone from Cadence wants to look into this also
since they are connection partners. This is directly from TYCO
Silverstorm P/N 310034-000 Rev 0
Investigate/Document CAD netlist issue
After analyzing the data and the CAD netlist files, I
have found that all the issues were caused by translation errors.
Most of these have to do with the format of the buried
resistor networks and blind vias in the netlist text file.
I've detailed the issues below for customer information,
but I'm approving the CAD netlist as verified to Gerber data.
Part of the resistor network contains the pad the
resistor is tied to:
307MN_DQ31 R543 -2 P
Our input is interpreting this as access side bottom, and
creating issues when this runs into features on the bottom side. Due to the
method of analysis in the Valor software this generates both shorted and broken
Removing these lines from our file eliminates both
Originally posted in cdnusers.org by firstname.lastname@example.org