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 Shorting 2 nets by a via in Schematic 

Last post Mon, May 15 2006 6:29 AM by archive. 5 replies.
Started by archive 15 May 2006 06:29 AM. Topic has 5 replies and 1597 views
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  • Mon, May 15 2006 6:29 AM

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    Shorting 2 nets by a via in Schematic Reply

    I want to short two nets (analog and digital ground) by a via. In schematic, how can I create such symbol which has one pin but attaching two different nets?

    Thanks in advance!


    Originally posted in cdnusers.org by Azure
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  • Mon, May 15 2006 7:35 AM

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    RE: Shorting 2 nets by a via in Schematic Reply

    I don't know about in the schematic, but you can attach the "Net Short" property to the via in the board file.


    Originally posted in cdnusers.org by Randy R.
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  • Mon, May 15 2006 8:29 AM

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    RE: Shorting 2 nets by a via in Schematic Reply

    Here is the source link solution number 11144408.
    this does work I have used it for a few years.

    Problem statement:

    I am creating my schematic design in Capture and using Allegro for my board layout.
    I have two nets "GND" and "AGND" in the schematic. I want to be able designate a
    specific point in the board layout where I will allow these two nets to be shorted
    (without generating a design rule error marker). I know how to use NET_SHORT in the
    ConceptHDL-to-Allegro flow to accomplish this. Can NET_SHORT also be used in the
    Capture-to-Allegro flow and, if so, how do I do this?

    Solution:

    You can use NET_SHORT in the Capture to Allegro flow also.

    In the following example I have a one pin component in my Capture schematic. The sole
    purpose of this one pin "component" is to provide a point where net "AGND" will be
    allowed to short to net "GND". The component has a reference designator of SP1 and a
    PCB Footprint of SHORTINGPOINT. Pin one of SP1 is tied to net "GND".

    1). Add the NET_SHORT property
    Add the NET_SHORT property to the pin of the component instance. Take care to be sure to
    select the pin of the component rather than the attached wire or the component itself.

    Make the value of the NET_SHORT property GND:AGND. The first netname in the value string
    is the net that the pin is connected to (GND in this case). The second netname in
    the value string is the net (AGND) that I wish to allow to short to GND at this
    point. The netnames are separated by a colon.

    2). Set up the allegro.cfg file
    Save the schematic and select Tools -> Create Netlist -> Allegro. Before netlisting
    select the Setup button on the Create Netlist form and choose the allegro.cfg file
    to be edited. The allegro.cfg file is loaded into a plain text editor. Locate the
    section called [pinprops] typically towards the bottom of the file. Add the line
    NET_SHORT = YES to this section. Save the allegro.cfg file and OK the Setup form.
    Then run the netlister by OK'ing the Create Netlist form.

    3). View the results in Allegro
    After netlisting is completed successfully, import the netlist into the Allegro board.
    Place component SP1 and place other components including pins of the net AGND. With
    Bubble Mode set to Off (instead of Hug Preferred or Shove Preferred) start a cline
    (add connect) at an AGND pin and draw the cline into the pin of component SP1. No
    DRC marker is reported even though the cline is on net AGND and the pin of SP1 is on
    net GND. Allegro ignores the violation because of the NET_SHORT property.

    Steve


    Originally posted in cdnusers.org by swilber
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  • Tue, May 16 2006 2:31 AM

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    RE: Shorting 2 nets by a via in Schematic Reply

    Quite useful! Thanks a lot!


    Originally posted in cdnusers.org by Azure
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  • Mon, May 29 2006 7:06 AM

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    RE: Shorting 2 nets by a via in Schematic Reply

    A further question is, the solution suggested by Swilber is only useful for shorting two nets on routing layer, how to make it work on power plane? Thanks!


    Originally posted in cdnusers.org by Azure
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  • Tue, May 30 2006 8:25 AM

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    RE: Shorting 2 nets by a via in Schematic Reply

    What I do is create a test point footprint called shortpoint.

    Place a 1 pin connector for each (shape) point you want to short together in the schematic,
    such as Agnd and Dgnd and assign the shortpoint footprint to that part.

    Then I assign the net_short property as described previously.

    Place the footprint on the board.
    There are a couple of problem in allegro.
    1) the second plane (positive) does not automatically connect.
    2) You must go use a Cline that goes from the shape to the short point footprint.
    3) And if you edit or connect to those planes the shortpoint cline is removed, (so I connect the shortpoint cline just before
    I generate the artwork).

    Steve


    Originally posted in cdnusers.org by swilber
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Started by archive at 15 May 2006 06:29 AM. Topic has 5 replies.