Here is the source link solution number 11144408.Originally posted in cdnusers.org by swilber
this does work I have used it for a few years.
I am creating my schematic design in Capture and using Allegro for my board layout.
I have two nets "GND" and "AGND" in the schematic. I want to be able designate a
specific point in the board layout where I will allow these two nets to be shorted
(without generating a design rule error marker). I know how to use NET_SHORT in the
ConceptHDL-to-Allegro flow to accomplish this. Can NET_SHORT also be used in the
Capture-to-Allegro flow and, if so, how do I do this?
You can use NET_SHORT in the Capture to Allegro flow also.
In the following example I have a one pin component in my Capture schematic. The sole
purpose of this one pin "component" is to provide a point where net "AGND" will be
allowed to short to net "GND". The component has a reference designator of SP1 and a
PCB Footprint of SHORTINGPOINT. Pin one of SP1 is tied to net "GND".
1). Add the NET_SHORT property
Add the NET_SHORT property to the pin of the component instance. Take care to be sure to
select the pin of the component rather than the attached wire or the component itself.
Make the value of the NET_SHORT property GND:AGND. The first netname in the value string
is the net that the pin is connected to (GND in this case). The second netname in
the value string is the net (AGND) that I wish to allow to short to GND at this
point. The netnames are separated by a colon.
2). Set up the allegro.cfg file
Save the schematic and select Tools -> Create Netlist -> Allegro. Before netlisting
select the Setup button on the Create Netlist form and choose the allegro.cfg file
to be edited. The allegro.cfg file is loaded into a plain text editor. Locate the
section called [pinprops] typically towards the bottom of the file. Add the line
NET_SHORT = YES to this section. Save the allegro.cfg file and OK the Setup form.
Then run the netlister by OK'ing the Create Netlist form.
3). View the results in Allegro
After netlisting is completed successfully, import the netlist into the Allegro board.
Place component SP1 and place other components including pins of the net AGND. With
Bubble Mode set to Off (instead of Hug Preferred or Shove Preferred) start a cline
(add connect) at an AGND pin and draw the cline into the pin of component SP1. No
DRC marker is reported even though the cline is on net AGND and the pin of SP1 is on
net GND. Allegro ignores the violation because of the NET_SHORT property.