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 Best practices for schematic pins connected to multiple package pins 

Last post Wed, Mar 22 2006 4:57 PM by archive. 8 replies.
Started by archive 22 Mar 2006 04:57 PM. Topic has 8 replies and 1803 views
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  • Wed, Mar 22 2006 4:57 PM

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    Best practices for schematic pins connected to multiple package pins Reply

    I am new to Cadence SPB/Allegro, so there may be something simple I'm missing.
    I am trying to set up some basic library components, such as an LM317 regulator.  The regulator comes in two styles we may use, a TO220 with 4 pins (3 pins and the heatsink), and a D-PAK with 3 pins.  In the TO220 package, pins 2 and 4 (the heatsink) are the same.  I want a schematic symbol with 3 pins connected to both possible footprints.

    In Part Developer, I can only connect a schematic pin to multiple footprint pins if I set it as a global pin, but then, as far as I can tell, I can't make it show up in the schematic symbol.  Alternatively, I can create a footprint with the same pin number for pin 2 and the heatsink (maybe?), but then I can't reuse the footprint between components. 

    Is there a better solution I'm missing?


    Originally posted in cdnusers.org by colincross
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  • Wed, Mar 22 2006 5:23 PM

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    RE: Best practices for schematic pins connected to multiple package pins Reply

    If I understand what you need, you wish to short pins 2 & 4 on the
    footprint to a single pin on the schematic device.

    Please review the attached document and see if this helps.

    Essentially, you'll be adding a PACK_SHORT property to the symbol.


    Jerry


    Originally posted in cdnusers.org by geraldg
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  • Wed, Mar 22 2006 5:27 PM

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    RE: Best practices for schematic pins connected to multiple package pins Reply

    You may also consider the SourceLink Solution# 1816165


    Jerry


    Originally posted in cdnusers.org by geraldg
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  • Wed, Mar 22 2006 5:32 PM

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    RE: Best practices for schematic pins connected to multiple package pins Reply

    Posted By geraldg on 3/22/2006 5:27 PM
    You may also consider the SourceLink Solution# 1816165

    Jerry
    Sorry - Please use this SourceLink direct link for Solution# 1816165

    http://sourcelink.cadence.com/docs/db/kdb/1998/July/1816165.html

    Jerry


    Originally posted in cdnusers.org by geraldg
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  • Thu, Apr 20 2006 1:28 PM

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    RE: Best practices for schematic pins connected to multiple package pins Reply

    Thanks for the link, it solves half my problem.
    However, the result of following the instructions is to create a symbol that looks like it has only 3 pins, but actually has 4, which can then be associated with a footprint with 4 pins.  The resulting symbol then cannot be used with a 3 terminal footprint.  Is there any way to create a single, 3 pin transistor symbol that could allow either a 3 pin SOT-23 footprint or a 4 pin TO220 footprint to be chosen from a part table file, or do I have to suck it up and make two parts in my library?


    Originally posted in cdnusers.org by colincross
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  • Thu, Apr 20 2006 1:40 PM

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    RE: Best practices for schematic pins connected to multiple package pins Reply

    Well ... from what you're trying to accomplish, this cannot even be considered
    an asymmetrical part. Since you needed to match either a 3 --or-- 4 pin
    physical package, the cleanest method would be to make 2 different components
    and reference their respective JEDEC_TYPE values for the footprints via the
    PTF files.

    Jerry


    Originally posted in cdnusers.org by geraldg
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  • Thu, Apr 20 2006 2:17 PM

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    RE: Best practices for schematic pins connected to multiple package pins Reply

    By components, do you mean two different cells in my library?  I've tried every combination of multiple symbols, pack types, and JEDEC_TYPE entries in a PTF file I can think of in a single cell, and nothing will package correctly.  I would really like to avoid creating two library cells, as that will cause confusion for users of my library down the road.


    Originally posted in cdnusers.org by colincross
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  • Thu, Apr 20 2006 2:45 PM

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    RE: Best practices for schematic pins connected to multiple package pins Reply

    Correct - 2 completely different cells/parts/folders in your library.

    So, your designers would add one part (cell) for the 3 pin device and
    a different part (cell) for the 4 pin device.

    Jerry


    Originally posted in cdnusers.org by geraldg
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  • Fri, Mar 16 2007 4:09 AM

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    RE: Best practices for schematic pins connected to multiple package pins Reply

    Hello All.

    I found this thread about an old problem. We succeed now to get only one Concept symbol for different pin number devices.
    (for exemple, regulator LP3961 from NATIONAL (5 on SOT223 or 6 pins TO220/263..)
    I also use the PACK_SHORT feature to allow the tab to be connected automatically to the net (GND for this LP3961, but more efficiently to VIN on some other regulators.)
    The problem is that we have to get the TAB pin on the body.
    It put it off-grid to avoid connecting a routing wire to the pin dot accidentally.
    If you connect a TAB pin (pack_shorted to GND) on VIN for example, VIN and GND will ne tied together!
    Really dangerous!!
    Is there a solution to get an error if it happens?
    How to prevent the TAB connection to something else than the net we want?

    I can't find the test3_archive (or multipin.tar) they spoke about in solution 1816165 at Sourcelink....


    Originally posted in cdnusers.org by willbi
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Started by archive at 22 Mar 2006 04:57 PM. Topic has 8 replies.