I am a Product Manager with Valor Computerized Systems, working closely with Cadence, and am trying to get information from the Allegro user base.
I have received a request from a Cadence Allegro user to support embedded passives in the Allegro-Valor ODB++ interface, and I would like to hear from other Allegro users that are designing pcb's with embedded passive content, or considering such designs in the future.
It is my understanding that although Allegro doesn't 'officially'
support embedded passives, and there are no internal guidelines, it is such a flexible PCB design tool that there are users who are creating such designs, and that one user has written a process for Allegro users.
The link to this process is:
Because each user could implement embedded passive support in different ways it may be difficult to implement Allegro ODB++ support. Therefore I would like to hear from interested users and perhaps explore the feasibility of adopting a generic design guideline.
ThanksOriginally posted in cdnusers.org by paulbarrow