In addition to what Mike mentioned, it is advantageous to ensure that your via and/or thru-pin padstack surface pads are large enough to accommodate test probes and that they are not solder-mask encroached when they will be used for test. In my experience a 35 mil minimum diameter surface pad is usually desired but 30mils may be acceptable for some test vendors. The minimum testpad spacing, center to center, is usually 50mils but should not be the nominal. 100mil spacing is much more desirable. Test pad density must also be considered. The goal is to provide test probe access for 100% of the nets, but this may not always be possible. Another way to help ensure that all nets are testable is to fanout all pins of SMD/BGA devices. This is not a guarantee that they will be testable, but will certainly help. Originally posted in cdnusers.org by rb
The bottom line is that you will still need to consult with your test fixture vendor for specific DFT requirements.