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 keepout question 

Last post Mon, May 9 2005 11:07 AM by archive. 3 replies.
Started by archive 09 May 2005 11:07 AM. Topic has 3 replies and 797 views
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  • Mon, May 9 2005 11:07 AM

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    keepout question Reply

    I want to create a bottom keepout area:
    -no bottom component placement
    - no vias
    -no bottom etch

    I've created a bottom keepout area:
    when I place a through hole e-cap on the top I don't get any DRC error.

    How can I get a DRC error when a through hole component is placed on the top?

    Thanks,


    Originally posted in cdnusers.org by mihaii
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  • Mon, May 9 2005 1:02 PM

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    RE: keepout question Reply

    You need to put bottom side place bound shapes on your symbol pads. Give them the maximum protrusion of your pins (2mm?)


    Originally posted in cdnusers.org by nzdave
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  • Mon, May 9 2005 2:34 PM

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    RE: keepout question Reply

    This sounds complicated. Is there a easier answer to my problem?
    I assumed Allegro to be smart and realize when a symbol has through hole components and give me a DRC error.


    Originally posted in cdnusers.org by mihaii
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  • Sun, May 22 2005 11:41 PM

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    RE: keepout question Reply

    Defining PLACE_BOUND_TOP shapes in your package symbols is a standard part of good library development. Every through-hole part is also present on the second side of the PCB (where the leads protrude or are clinched perhaps). Therefore it is good library development practice to define PLACE_BOUND_BOTTOM shapes describing these areas where the leads are present. Incorporating this as part of your lib development process requires very little extra time and will address your immediate problem.


    Originally posted in cdnusers.org by AshCan
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Started by archive at 09 May 2005 11:07 AM. Topic has 3 replies.