This can be handled in concept by using the net_short property so it will package, but this doesn't quide or help the Allegro designer. What is the best way to implement a sense line to a DUT pin and allow it to be a separate net until it connects to the power pin of the DUT. The use of single pin connector or zero ohm series resistors have limitations when wanting to use a shielded interlayer. Originally posted in cdnusers.org by firstname.lastname@example.org
Anything I can think of in concept just makes the packager work, but doesn't isolate the net so that the sense line can run through the voltage plane, and be voided. Is there is best solution?