Originally posted in cdnusers.org by andrewjw
In ConceptHDL you can either add the properties to a net/component directly (Edit->Properties), or you use the Constraint Manager to add some, but not all, properties.
Typically you don't enter any actual physical or spacing values in ConceptHDl but rather add a property that bundles all the nets together, then in Allegro PCB you create the constraints and assing these constraints to the different bundles (or classes) of nets.
For example, say you have a address bus that you wanted to add spacing rules to - in ConceptHDL you'd attach a property called NET_SPACING_TYPE = ADDR to all the required nets (either manually or using the Constarint Manager - this porperty can be attached to a bus and all bits will inherit the rule). This will bundle all the nets together, then when the design is drivien into Allegro, using the Constraint System Master you'd create a Spacing constraint set for ADDR and then use the Assignment table to map the Spacing rule to the bundle of nets (ADDR).
This does sound a long winded method but it can be very good and allows for different spacings to different nets as well as having different rules for areas on the brd. The same method applies for Physical constraints (minimum/max line width, neck width/length etc).