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 Creepage & clearance distances 

Last post Wed, Jul 6 2005 3:55 PM by archive. 3 replies.
Started by archive 06 Jul 2005 03:55 PM. Topic has 3 replies and 1068 views
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  • Wed, Jul 6 2005 3:55 PM

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    Creepage & clearance distances Reply

    I am about to begin a design which has many creepage distance and clearance distance requirements.
    Can I attach properties to signal traces in Concept for Allegro to use during layout?
    If so, please enlighten me as to the procedure. Thanks.


    Originally posted in cdnusers.org by wa7jos
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  • Fri, Jul 15 2005 9:44 PM

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    RE: Creepage & clearance distances Reply

    Sure, it's actually pretty easy.

    Are you familiar with setting constraints in Allegro? You will need to set up several types of clearance classes in the constraints editor. Probably need to set a physical constraint class too.

    Then be sure to set the rules up that tell Allegro which classes to use.

    There are a lot more tricks to doing creepage clearance but I hope this gives you a start.


    Originally posted in cdnusers.org by redwire
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  • Tue, Aug 1 2006 10:18 AM

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    RE: Creepage & clearance distances Reply

    i think you can use contraint manager and enter those values there and update in schematic for allegro


    Originally posted in cdnusers.org by nikhilbny
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  • Wed, Aug 2 2006 12:55 AM

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    RE: Creepage & clearance distances Reply


    In ConceptHDL you can either add the properties to a net/component directly (Edit->Properties), or you use the Constraint Manager to add some, but not all, properties.

    Typically you don't enter any actual physical or spacing values in ConceptHDl but rather add a property that bundles all the nets together, then in Allegro PCB you create the constraints and assing these constraints to the different bundles (or classes) of nets.

    For example, say you have a address bus that you wanted to add spacing rules to - in ConceptHDL you'd attach a property called NET_SPACING_TYPE = ADDR to all the required nets (either manually or using the Constarint Manager - this porperty can be attached to a bus and all bits will inherit the rule). This will bundle all the nets together, then when the design is drivien into Allegro, using the Constraint System Master you'd create a Spacing constraint set for ADDR and then use the Assignment table to map the Spacing rule to the bundle of nets (ADDR).

    This does sound a long winded method but it can be very good and allows for different spacings to different nets as well as having different rules for areas on the brd. The same method applies for Physical constraints (minimum/max line width, neck width/length etc).


    Originally posted in cdnusers.org by andrewjw
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Started by archive at 06 Jul 2005 03:55 PM. Topic has 3 replies.