Home > Community > Forums > PCB Design > processor to L3_cache interface

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 processor to L3_cache interface  

Last post Tue, May 29 2007 6:01 AM by archive. 2 replies.
Started by archive 29 May 2007 06:01 AM. Topic has 2 replies and 589 views
Page 1 of 1 (3 items)
Sort Posts:
  • Tue, May 29 2007 6:01 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    processor to L3_cache interface Reply

    Hey all

    In my design i am having processor to L3_cache interface in that  for Echoclock signal  going from L3_cache to processor when i did SI   i am getting Monotancity FAILs, i tryed to vary the length and resistor value even also i am not getting the result as PASS. my processor is at 2.5V and L3_Cache is at 1.5 v mode i selected  proper model for Simulation.
    I am attaching the topology file any one can suggest me what i have to do next.


    Originally posted in cdnusers.org by prashanthkumar.tm
    • Post Points: 0
  • Tue, May 29 2007 10:45 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: processor to L3_cache interface Reply

    It's odd you would see this behavior with only one load. Note that monotonicity is not a concern for a synchronous signal, but it seems you're saying this is a clock. I would move the resister closer to the driver (to the TOP layer) and possibly remove it. Since you have a 1.5V part driving a 2.5V part, it's possible you're not even reaching the Vih required by the 2.5V part (and hence the FAIL). In that case, you'd have to either add a pullup resistor (assuming the L3 output could handle it) or find a more suitable L3 part.

    Hope that helps,
    Donald


    Originally posted in cdnusers.org by Donald Telian
    • Post Points: 0
  • Thu, May 31 2007 9:42 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: processor to L3_cache interface Reply

    Thank you


    Originally posted in cdnusers.org by prashanthkumar.tm
    • Post Points: 0
Page 1 of 1 (3 items)
Sort Posts:
Started by archive at 29 May 2007 06:01 AM. Topic has 2 replies.