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 Package model 

Last post Tue, Apr 17 2007 12:12 PM by archive. 4 replies.
Started by archive 17 Apr 2007 12:12 PM. Topic has 4 replies and 727 views
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  • Tue, Apr 17 2007 12:12 PM

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    Package model Reply

    Hi In one of my IBIS files, I have the R,L,C_pkg as 0, and have another .rlc file which gives the package model. Is it possible to include this .rlc file in simulation with IBIS models? Thanks Pramod


    Originally posted in cdnusers.org by pramod_si
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  • Wed, Apr 18 2007 10:35 AM

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    RE: Package model Reply

    One way is to merge the IBIS file and the package file as follows
    |************************************************************************
    | Component my_device
    |************************************************************************
    [Component] my_device
    [Manufacturer] xyznetworks Inc.
    [package]
    | variable typ min max
    R_pkg 70.00m NA NA
    L_pkg 1.20nH NA NA
    C_pkg 2.1pF NA NA
    |
    [Package Model] compiled_pkg
    |
    [Pin] signal_name model_name R_pin L_pin C_pin
    |
    ...

    8.75000e-09 8.06985e-01 6.83135e-01 7.55377e-01
    |
    |
    | End Model SSTL18_50
    |
    [Define Package Model] compiled_pkg
    [Manufacturer] xyznetworks
    [OEM] Coresim
    [Description] xls2pkg
    [Number Of Sections] 2
    [Number Of Pins] 781
    [Pin Numbers]
    |
    |List |

    N33 Len=0 L =1.67nH C =0.44pF/
    Len=1 L=12.53nH C=3.01pF R=751.55m /
    L33 Len=0 L =1.3nH C =0.34pF/
    Len=1 L=9.71nH C=2.33pF R=582.33m /
    P33 Len=0 L =0.97nH C =0.25pF/
    ...


    Originally posted in cdnusers.org by Kalevi2
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  • Wed, Apr 18 2007 10:45 AM

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    RE: Package model Reply

    Hi Keskinen
    Thanks for ur response.
    This is the way I did the simulation. Pls comment if it makes sense.
    Since I have the IBIS model and a seperate package model which is a three line model, I converted that 3 line model to ESPICE black box using MI and used that after the buffer model for the IC. Will this be ok? Will this take care of the package parasetics of the chip? Pls comment.
    Thanks
    Pramod


    Originally posted in cdnusers.org by pramod_si
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  • Wed, Apr 18 2007 11:00 AM

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    RE: Package model Reply

    Your apporach is fine for SigXP simulations. You should hook up 3 buffer pins to the black box on the device side and either terminate with 50 Ohms to ground the unused buffers on the board side or you can do cross-talk studies with all 3 buffers driving (use custom stimulus to obtain odd and even cross-talk) and terminated into the approriate transmission lines (coupled or uncoupled as needed) with Rx buffers at the end of the lines.


    Originally posted in cdnusers.org by Kalevi2
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  • Wed, Apr 18 2007 11:05 AM

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    RE: Package model Reply

    Hi Keskinen
    Thank you very much for ur response. I will do the simulations as u suggested.
    Can I get ur email address pls?
    Thanks
    Pramod


    Originally posted in cdnusers.org by pramod_si
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Started by archive at 17 Apr 2007 12:12 PM. Topic has 4 replies.