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 Why equal length? 

Last post Fri, Jan 5 2007 10:38 PM by archive. 2 replies.
Started by archive 05 Jan 2007 10:38 PM. Topic has 2 replies and 526 views
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  • Fri, Jan 5 2007 10:38 PM

    • archive
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    Why equal length? Reply

    Hi all,

    I selected the SDRAM interface signal quality parameter with Kai’s help. But a new problem comes out. I have to determine the trace length limitation of the interface through timing analysis. I wonder whether my understanding is right.

     

    If the longest trace satisfies the timing analysis, there is no need to keep the data bus traces the same length. But it is said that the traces of the data bus should be equal length and the address bus also. Why? It confused me a long time.

     

    Are there any other limitations, such as data bus vs. DQM…?

    Would you please give me some suggestion?

     

    Thanks in advance.


    Originally posted in cdnusers.org by chenli
    • Post Points: 0
  • Fri, Jan 5 2007 10:56 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
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    RE: Why equal length? Reply

    Sorry! Please delete this thread.


    Originally posted in cdnusers.org by chenli
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  • Fri, Jan 5 2007 10:56 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,910
    RE: Why equal length? Reply

    Sorry! Please delete this thread.


    Originally posted in cdnusers.org by chenli
    • Post Points: 0
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Started by archive at 05 Jan 2007 10:38 PM. Topic has 2 replies.