Home > Community > Forums > PCB Design > Verilog Simulation in Board Flow for a FLAT schematic.

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Verilog Simulation in Board Flow for a FLAT schematic. 

Last post Mon, Jul 31 2006 1:14 AM by archive. 0 replies.
Started by archive 31 Jul 2006 01:14 AM. Topic has 0 replies and 465 views
Page 1 of 1 (1 items)
Sort Posts:
  • Mon, Jul 31 2006 1:14 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,950
    Verilog Simulation in Board Flow for a FLAT schematic. Reply

    Hi all,

    I'm not sure if this is the right section for my post. If not, please advice me the proper one.

    Our schematics are generated in ConceptHDL and are flat. My memory module contains a connector, few DRAMs and several passive devices. I have the correct behavioral models of my components. Is it possible to perform logic simulation of the whole schematic?

    My flat schematic seems the only obstacle. Currently I can simulate similer components (Drams)  in my design but soon as I try to connect them with other components e.g. connector , the setup fails due to pinmap (e.g. pin A0 in dram is defined INPUT while in connector it is INOUT).
     
    Has anyone sucessfully accomplished the verilog simulation flow in Board Design?

    Please help!

    Thanks,
    Saad.


    Originally posted in cdnusers.org by Saad
    • Post Points: 0
Page 1 of 1 (1 items)
Sort Posts:
Started by archive at 31 Jul 2006 01:14 AM. Topic has 0 replies.