Hi all,Originally posted in cdnusers.org by Saad
I'm not sure if this is the right section for my post. If not, please advice me the proper one.
Our schematics are generated in ConceptHDL and are flat. My memory module contains a connector, few DRAMs and several passive devices. I have the correct behavioral models of my components. Is it possible to perform logic simulation of the whole schematic?
My flat schematic seems the only obstacle. Currently I can simulate similer components (Drams) in my design but soon as I try to connect them with other components e.g. connector , the setup fails due to pinmap (e.g. pin A0 in dram is defined INPUT while in connector it is INOUT).
Has anyone sucessfully accomplished the verilog simulation flow in Board Design?