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 Should I worry about die signal overshoot? 

Last post Fri, Jun 16 2006 3:11 PM by archive. 10 replies.
Started by archive 16 Jun 2006 03:11 PM. Topic has 10 replies and 1540 views
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  • Fri, Jun 16 2006 3:11 PM

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    Should I worry about die signal overshoot? Reply

    I have a SigXplorer simulation showing overshoot at the die level for a mobile DDR (1.8V) device driven by a fairly new ARM11 device that violates the overshoot specification fr the memory.  However, the package pin shows no specific overshoot problem.  The trace length is less than 1/2 inch and the speed is 133MHz.  The trace is controlled impedance.  According to the memory vendor, they say their specification is for the waveform at the package pin.  But according to the CPU vendor and a high speed design consultant, they say that the signal performance at the die is also important.

    So, who do I believe?

    The simulation only fails the overshoot specification when the Simulation Modes is set to FTS Mode: Fast.  Typical and slow are fine.  Attached is the printout from the simulation.  Feel free
    to email me if you have a definitive answer.  Thanks in advance.


    Originally posted in cdnusers.org by fitzdean
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  • Mon, Jun 19 2006 8:39 AM

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    RE: Should I worry about die signal overshoot? Reply

    One thing to keep in mind is that the fast case is VccTypical+10%. If you take the magnitude of the overshoot and subtract from it the fast case Vcc and then add the typical case Vcc, do you still exceed the spec? What kind of package model do you have on this device?


    Originally posted in cdnusers.org by Kalevi2
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  • Mon, Jun 19 2006 8:43 AM

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    RE: Should I worry about die signal overshoot? Reply

    Signal performance at the die is the important thing since that is what the silicon sees. Since we cannot use a scope probe to access the die, timing numbers are referenced to the pin except rarely when you are provided detailed package delays.


    Originally posted in cdnusers.org by Kalevi2
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  • Tue, Jun 20 2006 8:23 AM

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    RE: Should I worry about die signal overshoot? Reply

    Yes, the simulation still would show violation if I subtracted off the 10% high on the VCC.


    Originally posted in cdnusers.org by fitzdean
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  • Tue, Jun 20 2006 8:31 AM

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    RE: Should I worry about die signal overshoot? Reply

    What kind of package model do you have?


    Originally posted in cdnusers.org by Kalevi2
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  • Tue, Jun 20 2006 10:42 AM

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    RE: Should I worry about die signal overshoot? Reply

    137 pin FBGA, 0.8mm pitch, stacked DDR/NAND, not sharing data bus.


    Originally posted in cdnusers.org by fitzdean
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  • Tue, Jun 20 2006 11:17 AM

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    RE: Should I worry about die signal overshoot? Reply

    What kind of package model do you have?


    Originally posted in cdnusers.org by Kalevi2
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  • Tue, Jun 20 2006 2:42 PM

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    RE: Should I worry about die signal overshoot? Reply

    how can I tell?  All I have is the IBIS model the memory vendor sent.


    Originally posted in cdnusers.org by fitzdean
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  • Wed, Jun 21 2006 3:55 AM

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    RE: Should I worry about die signal overshoot? Reply

    Dean:

    You can tell by looking at the IBIS model. Is there only 1 set of package RLC with typ, min, and max at the top of the pin list or are there pin specific RLCs (unique per pin) or is there a distributed or sparse matrix package model at the end of the ibis file?


    Originally posted in cdnusers.org by Kalevi2
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  • Wed, Jun 21 2006 1:06 PM

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    RE: Should I worry about die signal overshoot? Reply

    Kai,

    There is a [Package] at the beginning with R_pkg, L_pkg, and C_pkg
    followed by a pin list with R_pin, L_pin, and C_pin.


    Originally posted in cdnusers.org by fitzdean
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  • Wed, Jul 12 2006 12:05 PM

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    RE: Should I worry about die signal overshoot? Reply

    Hi Dean,

    It's true that the signal at the die is "important" and "what is actually seen by the device".  However, if the memory vendor has written their overshoot spec for the "package pin" then they have accounted for what the die will actually see.  It's common to spec things at points visible to the outside world.  You're using the simulator to "peak" at what is actually going on inside, but most people (particularly those with oscilloscopes!) can not see the waveshape there.  Consequently, IC vendors write specs for waveshapes at the pins.  They know what an overshoot at the pin can cause at the die and have derated their specs accordingly. 

    I'd say go with what/where each part vendor has spec'd. 

    Donald


    Originally posted in cdnusers.org by Donald Telian
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Started by archive at 16 Jun 2006 03:11 PM. Topic has 10 replies.