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 IBIS Model Issue 

Last post Tue, May 30 2006 11:27 PM by archive. 6 replies.
Started by archive 30 May 2006 11:27 PM. Topic has 6 replies and 1143 views
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  • Tue, May 30 2006 11:27 PM

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    IBIS Model Issue Reply

    I have a problem with a model supplied by an IC vendor. SQ does not produce the expected waveform, and produces the message"warning - waveform contains less than the requested 1 cycle". By trial and error, I've determined that the problem is with the rising waveform with Vfixture = 0 - if I comment out part of this, the problem goes away. The problem waveform is attached.

    Can anyone tell me why this is happening, and what the SQ warning means ?

    Thans


    Originally posted in cdnusers.org by aball
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  • Fri, Jun 2 2006 9:05 AM

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    RE: IBIS Model Issue Reply

    Aball,
    The warning message is about the measurement due to bad waveforms.

    About VT waveforms, I don't think it will be a problem for Vfixture=0 or not. I couldn't figure out from your attached file for the issues but I guess something wrong with VI and VT curve mismatch.


    Originally posted in cdnusers.org by lwang
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  • Tue, Jun 6 2006 4:17 AM

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    RE: IBIS Model Issue Reply

    It is quite common to get IBIS models where the I-V and V-t curves have some inconsistency that leads to problems with the simulation engine. Removing the v-t curves (or one set of curves) fixes this but you lose some accuracy. The warning message from the tool is telling you that the signal did not cross the threshold for the required number of pulses that you had selected.


    Originally posted in cdnusers.org by Kalevi2
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  • Tue, Jun 6 2006 12:34 PM

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    RE: IBIS Model Issue Reply

    Kai/Lance

    Thanks for your help - I'm a bit of an IBIS novice, as you will have gathered, so I was a bit nervous about removing part of the model, however I think the part I've removed will have limited effect on the results.

    Bit disappointing to use a model from a major IC vendor, and a simulator from a major CAD vendor, and find them incompatible/not tested together - this was quite a fundamental and obvious fault - perhaps I'm being unrealistic

    Thanks again


    Originally posted in cdnusers.org by aball
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  • Tue, Jun 6 2006 8:15 PM

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    RE: IBIS Model Issue Reply

    Aball,
    IBIS model has its own rules for syntax and usages. When it is broken, we called it "Bad" model. Simulator always play "Gabage in, gabage out" rule since it will not be able to find the way to fix them. So, to use kai's comment about VT and IV curve inconsistant issue as an example, if IBIS model is bad, it is not the problem for the simulator. but it is model self. It must be fixed. When you have a bad model no matter it is IBIS, Spice, S-parameters, VHDL or others, simulator will not give you the answers that you expected no matter simulator is from Cadence or Mentor or Synopsis or other vendors.
    By saying this, Good model is the MUST requirement to get correct results from simulations. Don't complain the simulator first, but needs to check whether your models are good first.


    Originally posted in cdnusers.org by lwang
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  • Wed, Jun 7 2006 3:58 AM

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    RE: IBIS Model Issue Reply

    Aball:

    It is common to find IBIS models from large or small companies that sometimes do not even pass the syntax checks. Models that pass the checks are not necessarily tested. Some companies actually provide a comparison between the HSPICE model and the IBIS model showing good correlation. The chip vendors are in the business of making chips. Creating IBIS models is not a core function and they are often not given the attention we SI people feel they need. Chances are good that your particular model would also give you convergence errors in HSPICE. Deleting the v-t curves brings you back to IBIS 1.0. IBIS 2.1 brought out the V-T curves. Two sets of V-T curves are better for accuracy. If you do some searching, you will find papers that show comparisons between only using ramp info and using v-t curves.


    Originally posted in cdnusers.org by Kalevi2
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  • Wed, Jun 7 2006 3:58 AM

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    RE: IBIS Model Issue Reply

    Aball:

    It is common to find IBIS models from large or small companies that sometimes do not even pass the syntax checks. Models that pass the checks are not necessarily tested. Some companies actually provide a comparison between the HSPICE model and the IBIS model showing good correlation. The chip vendors are in the business of making chips. Creating IBIS models is not a core function and they are often not given the attention we SI people feel they need. Chances are good that your particular model would also give you convergence errors in HSPICE. Deleting the v-t curves brings you back to IBIS 1.0. IBIS 2.1 brought out the V-T curves. Two sets of V-T curves are better for accuracy. If you do some searching, you will find papers that show comparisons between only using ramp info and using v-t curves.


    Originally posted in cdnusers.org by Kalevi2
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  • Tue, Jun 13 2006 1:04 PM

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    RE: IBIS Model Issue Reply

    The problem mentioned typically means that the logic thresholds are missing in the receivers, hence the waveform doesn't ever appear to "switch".  So the tool thinks the "cycles" didn't happen.  If you're just looking at waveforms, the warning typically can be ignored.  But if you're doing automated cycle-based measurements/reports, you'll need to add the thresholds so the tool can count cycles.

    Donald


    Originally posted in cdnusers.org by Donald Telian
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Started by archive at 30 May 2006 11:27 PM. Topic has 6 replies.