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 Some topics for discussion 

Last post Sun, Mar 5 2006 6:48 AM by archive. 0 replies.
Started by archive 05 Mar 2006 06:48 AM. Topic has 0 replies and 539 views
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  • Sun, Mar 5 2006 6:48 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,950
    Some topics for discussion Reply

    Hi Folks:

    This forum is to discuss Signal Integrity issues that are not model related. Model related issues should be posted in the Modeling forum  but there is a strong overlap.  The forum  is also not intended to replace SourceLink but getting a quick answer to some tool related issue is OK. Most of you who are registered are Cadence users and so much of our discussions will be focussed around the Cadence tools. I encourage all of you to sign up for the [SI-LIST] which has many interesting discussions and is a constant source of useful web links and information. I'd like to bring up some topics for discussion:

    I run what is basically a Signal Integrity service bureau performing SI work for both internal and external customers. I have dealt with well established companies that have had SI in the design flow for many years but we are still encountering established companies that are just beginning to introduce SI into their design flow. Most startups recognize that they need to perform SI analysis to ensure that they get their design right the first time so they can make their market window. The cost benefit analysis of spending the time and money up front to get the design right for the first spin of the board or doing two or more iterations with weeks of debugging is obvious. Why are so many design managers and sometimes their managers still reluctant to fund the SI analysis? It seems more important to make the planned board build date than to get it done right. Can anyone desribe their experiences with this kind of thing?

    Another issue is how to speed up the process of performing a comprehensive SI and STA analysis on the key interfaces. I find that interfaces such as DDR and the high speed differential are very quick to analyze while things like 60x busses and PCI busses take lots of time. Has anyone else had similar experiences?

    How many of you are students? If you have a career in SI engineering, you should have very few times in your life when you are unemployed. The jobs are usually not posted but there are many jobs out there. Quite a few EE departments now offer courses in SI. Design cycle times are still shrinking and new chipsets and technologies come faster than designers can keep up with them. There are very few designers who have  the time to do a proper SI and STA analysis for their boards so they have to rely on a supporting SI Engineer or engineers. Is there anyone out there who is a true board designer who has the time to actually do the SI and STA for their designs?

    What are your favourite books?

    1) Howard Johnson's "Handbook of Black Magic" was the probably the first book that focusses purely on SI at a practical level and is still a must have.

    2) My favourite book is "High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices" by Stephen H. Hall, Garrett W. Hall, James A. McCall. They cover many areas of SI including STA in reasonable depth without getting bogged down in theory.

    3) Bryan Young's book "Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages" is really good for getting started in modeling.

    4) The section on power by John Zasio in "Right the First Time, A Practical Handbook on High Speed PCB and System Design, Volume 1," is excellent and very well complements the Power Integrity option of Allegro PCB SI.

    Anyone have other books that they  like because they are useful instead of just giving a shallow overview that leaves you with more questions than answers?

    Enough for now. Let's get into some discussions about SI.


    Originally posted in cdnusers.org by Kalevi2
    • Post Points: 0
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Started by archive at 05 Mar 2006 06:48 AM. Topic has 0 replies.