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 Points of load Simulation 

Last post Mon, Nov 28 2005 10:55 PM by archive. 0 replies.
Started by archive 28 Nov 2005 10:55 PM. Topic has 0 replies and 391 views
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  • Mon, Nov 28 2005 10:55 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
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    Points of load Simulation Reply

    Hi
    I know the theory of points of load on PCB.
    They should be as close as possible to the CPU or FPGA and regulated without any interferences.
    My question is that if it is acceptable to use power supply with the points of load on it.
    I need to use 5V, 3.3V, 2.5V and 1.5V.
    The 2.5 and 1.5 are the points of load, but I want to design them on the power supply as isolated power.
    And route 10 inches long 1/4 width conductors for these powers and put few low ESR capacitors near the CPU/FPGA.
    Any recommendations?
    Is it acceptable?
    Can I simulate this case?


    Originally posted in cdnusers.org by dadi_matza
    • Post Points: 0
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Started by archive at 28 Nov 2005 10:55 PM. Topic has 0 replies.