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 Double-counting issue of IBIS model 

Last post Sun, Jul 3 2005 11:24 PM by archive. 1 replies.
Started by archive 03 Jul 2005 11:24 PM. Topic has 1 replies and 578 views
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  • Sun, Jul 3 2005 11:24 PM

    • archive
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    Double-counting issue of IBIS model Reply

    Hi,

    As I know, PCB SI is able to process double-couting issue of IBIS model. But, how about Dual-Core case and/or Dual-Processor? In case of complex test load, is it able to define the arbitrary test load by user? Thank you in advance.

    BRs,

    Sogo Hsu, Ph. D.
    Foxconn


    Originally posted in cdnusers.org by sogohsu
    • Post Points: 0
  • Mon, Aug 1 2005 9:35 AM

    • archive
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    RE: Double-counting issue of IBIS model Reply

    Hi, Sogo,
    Just saw your question.

    1. about dual-core or daul-processor question, I think it will depends on what you have. If it fits IBIS's methodologies, PCB SI should be able to handle it;
    2. About complex test-loads, for now, DML(Cadence's device model) can have self-define test-loads for differential pairs. In the near future, DML will be able to use self-define single-end test-load as well.

    Hope this helps,

    Lance Wang


    Originally posted in cdnusers.org by lwang
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Started by archive at 03 Jul 2005 11:24 PM. Topic has 1 replies.