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 EBD file simulation 

Last post Mon, May 30 2005 8:26 PM by archive. 2 replies.
Started by archive 30 May 2005 08:26 PM. Topic has 2 replies and 1152 views
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  • Mon, May 30 2005 8:26 PM

    • archive
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    EBD file simulation Reply

    hi,
    I have a question in EBD file simulation with SpecctraQuest.The IC vendor affords ibis files and EBD files for modeling the chip package.How could I implement the simulation using EBD files in SQ? Should I carry out the simulation with multi-board modeling? If so, how can I extract the EBD file to build a brd file?

    Thanks!


    Originally posted in cdnusers.org by zhuofan
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  • Mon, May 30 2005 9:20 PM

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    RE: EBD file simulation Reply

    The ibis2signoise program can be used to convert the EBD models into either boardmodels or, in some cases, package models. If there is a single path, or more importantly a one to one map of the pins in the EBD to a single IOCell(not like a memory module, where one connector pin goes to many IOCells) then you can use the
    -ebdcomp switch when running ibis2signoise. This should then make a pkg model that you can use for the package. You build up the IBISDevice file as normal with the IOcells defined by the vendor, with the EBD converted package model assigned.

    If you don't use this route, then you need to convert the EBD into a boardmodel and use the designlink process to simulate. This approach has a caveat right now in that the boardmodel cannot be used to extract a accurate model into SigXP. Look for an appnote to be posted soon to address this issue in more detail


    Originally posted in cdnusers.org by horner
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  • Tue, May 31 2005 8:05 PM

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    RE: EBD file simulation Reply

    Thanks for your instant reply. The EBD just models the chip's package.I followed your instruction and translated the EBD file to a package model with ibis2signoise –ebdcomp command. Then I loaded the resulting IBISDevice model and assigned the model to the corresponding device. But some warning(some pin numbers are not defined in model) appeared, and some error occurred when I extract the net topology between this chip and other device. I found in the produced DML file, only chip die’s pin numbers exist, and there were no chip’s pin numbers description.But these pin numbers are present with boardmodel conversion method. Any other step should be done with the IBISDevice file?
    Thanks!


    Originally posted in cdnusers.org by zhuofan
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Started by archive at 30 May 2005 08:26 PM. Topic has 2 replies.