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 Net_nwell net_welltap DRC error 

Last post Thu, Jun 19 2008 1:15 AM by archive. 2 replies.
Started by archive 19 Jun 2008 01:15 AM. Topic has 2 replies and 2648 views
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  • Thu, Jun 19 2008 1:15 AM

    • archive
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    Net_nwell net_welltap DRC error Reply

    hello all,

    This seems a silly error however I've spent the last hour trying a variety of things to solve it but ultimately have been unsuccessful :(

    When I run DRC of my layout I get the errors,

    "net_nwell net_welltap : Has Multiple Stamped Connections"
    "net_nwell net_welltap : Causes Multiple Stamped Connections"

    When I zoom to markers Virtuoso flags a simple contact I have to an n well. I used the Create > Contact option for this simple contact (i.e. not hand drawn). Admitteldy the contact area is very big compared to typical CMOS contacts (I have 20 columns x 80 rows contact openings) but I do not see how this should matter.

    Does anyone know how to solve this frustrating issue?

    Many thanks,

    James


    Originally posted in cdnusers.org by jgrant3
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  • Thu, Jun 19 2008 1:29 AM

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    RE: Net_nwell net_welltap DRC error Reply

    James,

    Generally speaking this kind of error means that you have more than one well contact, with the metal connected to different nets. This means you've got a "soft connect" through the well (not quite a short, because the well is resistive). It may be that you're making a connection via the well, which is almost certainly not what you want!

    So check what other well contacts you have in the same well, and what they're connected to. If the connections are made in metal as well as nwell, the error will (most likely) go away.

    Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett
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  • Thu, Jun 19 2008 3:23 AM

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    RE: Net_nwell net_welltap DRC error Reply

    Hi Andrew, thanks for your comments.

    Within my nwell I have a vertical pnp bipolar transistor. The base region is connected to ground. I think this may be causing the problem since I have the (n-type) base of the vertical pnp transistor connected to ground while the rest of the nwell is connected to a different potential (N.B. the nwell will not be connected to vdd as is standard. My n well will be connected to a +ve potential but for the purpose of subsequent electrochemical etching). So I can see how Virtuoso/DIVA (whoever) can see my nwell is connected to 2 different potentials HOWEVER in actual operation of my circuit the nwell will not be connected to any potential. The vertical pnp bipolar transistor connections contained within my nwell will have the base and collector diode connected to ground.

    So I have two options:

    1. Somehow get DIVA to acknowledge that there are two connections to my nwell but in practice there will only be one (not sure how to do that) or

    2. Draw a second n well within my original n well and then within this second n well define my vertical pnp transistor. This way my two n-wells will have different potentials. However I'm not sure about parasitic transistors/pn junctions associated with this configuration.



    Originally posted in cdnusers.org by jgrant3
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Started by archive at 19 Jun 2008 01:15 AM. Topic has 2 replies.