Home > Community > Forums > Custom IC Design > How can Assura differentiate between drain and source of MOS transistor??

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 How can Assura differentiate between drain and source of MOS transistor?? 

Last post Wed, Sep 12 2007 8:09 AM by archive. 1 replies.
Started by archive 12 Sep 2007 08:09 AM. Topic has 1 replies and 1154 views
Page 1 of 1 (2 items)
Sort Posts:
  • Wed, Sep 12 2007 8:09 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    How can Assura differentiate between drain and source of MOS transistor?? Reply

    Hi,

    I have a question about assura (or LVS extractor in general), how can the tool determine if the pin is the "drain" or "source" of the transistor??

    Can I control that to get special output netlist (SPICE netlist)..??

    Thanks in advance,
    Ahmad


    Originally posted in cdnusers.org by ahmad_abdulghany
    • Post Points: 0
  • Wed, Sep 12 2007 2:20 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: How can Assura differentiate between drain and source of MOS transistor?? Reply

    I'm not really an expert but I believe the tool doesn't really make a distinction between source & drain. It simply matches nets in the device and the connectivity takes care of itself. Now if you are talking about a simple layout cell you are making for your individual device then I would create & place pins on the sorce & drain and make the labels match the pin names from the symbol view.


    Originally posted in cdnusers.org by bthayer
    • Post Points: 0
Page 1 of 1 (2 items)
Sort Posts:
Started by archive at 12 Sep 2007 08:09 AM. Topic has 1 replies.