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 Figure Causing Multiple Stamped Connections 

Last post Wed, Feb 15 2006 6:13 PM by archive. 2 replies.
Started by archive 15 Feb 2006 06:13 PM. Topic has 2 replies and 2248 views
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  • Wed, Feb 15 2006 6:13 PM

    • archive
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    Figure Causing Multiple Stamped Connections Reply

    Hi,

    I am university student currently learning Cadence tools. I use DIVA for DRC, Extract and LVS.

    Process : TSMC18RF (0.18um)

    I am currently doing layout of an 10 phase oscillator circuit. When I run DRC on my completed layout I get no errors. When I run Extract with the "Join nets with same name" switch ON and Parasitic RC Switch SET. I get the following errors:

    Figure Causing Multiple Stamped Connections
    Figure Having Multiple Stamped Connections

    if i set the Parasitic RC switch OFF - that is if dont set any switches ( no parasitic extract ) I DONT get these errors or ANY errors.

    My Design also passes the LVS succesfully

    my design has following layout structure:

    VDD Rail
    ====================
    BUFFER Amplifiers
    ====================
    GND Rail
    ====================
    Differential Amplifiers
    ====================
    VDD Rail
    ====================
    Buffer Amplifiers
    ====================
    GND Rail
    ====================

    I googled these error messages and I found some explanations but I dont seem to violate any that is mentioned in these expalnations. Like I have connected the GND and VDD properly.

    the divaEXT doesnt like me putting 2 separate ground Contacts. my Ground contacts are M1_SUB. if put them at separate places i get this error. How do I go about resolving this issue? please help.


    Originally posted in cdnusers.org by cAddIE
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  • Thu, Feb 23 2006 7:48 AM

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    RE: Figure Causing Multiple Stamped Connections Reply

    Typically the problem is that you cannot check for substrate connection when doing parasitic resistance extraction. You can not do this because the metal1 layer gets broken up into resistors (parasitic) so every metal1/ptie and metal1/ntie contact is on different net. Basically what you have are two well contacts that have different nodal information.

    Try changing the rule (geomStamp) in your divaEXT.rul file so it does not use the "error" keyword when parasitic resistance is in use.


    Originally posted in cdnusers.org by rhcdn
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  • Tue, Jul 11 2006 11:40 PM

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    RE: Figure Causing Multiple Stamped Connections Reply

    Another place to look is the p2lvs file. In this file you define (in the first line) which are your substrates and how are they "stamped" together. Personaly, I had many problems understanding all the options there till the end, but playing around with it might help.

    Ezra


    Originally posted in cdnusers.org by ecyashar
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Started by archive at 15 Feb 2006 06:13 PM. Topic has 2 replies.