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 Import Files for Encounter ( Preparing for Encounter)  

Last post Mon, Jul 28 2014 10:15 PM by Quek. 1 replies.
Started by Mr Aseem 20 Jun 2014 01:04 PM. Topic has 1 replies and 1470 views
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  • Fri, Jun 20 2014 1:04 PM

    • Mr Aseem
    • Not Ranked
    • Joined on Fri, Jun 20 2014
    • Posts 1
    • Points 20
    Import Files for Encounter ( Preparing for Encounter) Reply

     

    Hello

     

    I am using Cadence Virtuoso 6.1.2.

    Can you please guide me how to create .v files from a schematic ( lets say of an inverter)?

    Also, I wish to create .lef file of my standard cell layout design through Abgen.But I get error ABS 218 amd ABS - 262. I have fixed those errors, still it is a problem. Do you know any other way to get - 

     

    1.  .v files ( gate-level netlist - design files) 

    2   .lef files   ( layout info )

    3.  .lib files ( timing info )

    I need these files to start working on encounter. 
    • Post Points: 20
  • Mon, Jul 28 2014 10:15 PM

    • Quek
    • Top 10 Contributor
    • Joined on Wed, Oct 14 2009
    • Singapore, 00-SG
    • Posts 1,082
    • Points 16,475
    Re: Import Files for Encounter ( Preparing for Encounter) Reply

    Hi Aseem

    1. You can generate a verilog netlist from the schematic using "Launch->Simulation->NC-Verilog" function. This requires a license.

    2. You will need to use abstract generator to generate the lef file. Would you please provide more details on the errors?

    3. Please use a cell characterization tool such as Liberate.


    Best regards
    Quek

    • Post Points: 5
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Started by Mr Aseem at 20 Jun 2014 01:04 PM. Topic has 1 replies.