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 In UVM is there any Inheritance like "Specman e when Inheritance".. 

Last post Mon, Jun 16 2014 12:56 AM by Tudor Timi. 1 replies.
Started by Selvavinayak 14 Jun 2014 07:03 AM. Topic has 1 replies and 1047 views
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  • Sat, Jun 14 2014 7:03 AM

    • Selvavinayak
    • Not Ranked
    • Joined on Thu, May 10 2012
    • chennai, Tamil Nadu
    • Posts 11
    • Points 145
    In UVM is there any Inheritance like "Specman e when Inheritance".. Reply

    Hi all,

    I need following Information,

    In Specman e: 

      we are able to Create field  inside the struct like

    sample Code:

    when WRITE'trans_type

    {

      addr: uint[31:0];

    };
     

    when READ'trans_type

    {

      addr: uint[8:0];

    };
     

    In UVM:

      If I want to create a field in parent Class using Inheritance is Possible... I have Better Knowledge in Spceman e. I am new to UVM due to comparing those Environment feature I got this Doubt...

     

    Please any body Share your Knowledge to Update myself... 

     

    Thanks,

    Selvavinayakam.na

     

    • Post Points: 20
  • Mon, Jun 16 2014 12:56 AM

    • Tudor Timi
    • Not Ranked
    • Joined on Thu, Jul 25 2013
    • Neubiberg, Bavaria
    • Posts 14
    • Points 175
    Re: In UVM is there any Inheritance like "Specman e when Inheritance".. Reply
    To the extent of my knowledge, 'when' inheritance is unique to e. SystemVerilog only supports 'like' inheritance.
    • Post Points: 5
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Started by Selvavinayak at 14 Jun 2014 07:03 AM. Topic has 1 replies.