i designed a five stage ring osc,and each
stage is made up of an inverter. I perform DC analysis first,and I found
output voltage of each stage is at the half of VDD. Then I do stb
analysis ,founding that when the phase shift is 180,the gain is below
the 0dB. Which means that it can not oscsillate.But when I do tran ,it
oscillate at 1.3GHz,which is very weir.
My cadence version is IC615,MMSIM is 13.0
Does anyone could helpe me figure it out?Thanks any help in advance