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 How to define a binary matrix parameter in Verilog A 

Last post Wed, Jun 4 2014 2:29 AM by microstudent. 6 replies.
Started by microstudent 30 May 2014 12:33 AM. Topic has 6 replies and 2133 views
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  • Fri, May 30 2014 12:33 AM

    How to define a binary matrix parameter in Verilog A Reply

    Hi guys, I have a question about how to define a binary matrix parameter in Verilog A. For example, I can define parameter as data_pattern[15:0]={0,0,0,.....,0}. To my knowledge, each bit of data_pattern[15:0] are 32bit integer, for me I only want data_pattern to be a 16-bit binary.

    After run the code (attach on this post), the data_pattern[0] returned to be 0111111111111111111111111111111 instead of a 32bit "0", which makes the final verilog module incorrect.

     Also no matter how the data_pattern set throught cadence instantce interface, the output is still unchanged. Means the data_pattern parameter can not be changed without changing the code.

     Thank you for your help in advance!!


    • Post Points: 20
  • Mon, Jun 2 2014 2:48 AM

    Re: How to define a binary matrix parameter in Verilog A Reply

    Can you please post the actual code rather than a picture of it? I'd like to investigate, but don't particularly want to spend the time typing in your code from the picture. Something I can copy and paste from is much better.

    Help me to help you...

    Andrew.

    • Post Points: 20
  • Mon, Jun 2 2014 8:20 PM

    Re: How to define a binary matrix parameter in Verilog A Reply

    Hi Andrew,

                    Thank you very much for your reply! Here is the code:

    `include "constants.vams“
    `include "disciplines.vams"
    module data_pattern_gen(DATA,VDD,VSS);
    output [15:0] DATA; electrical [15:0] DATA;
    inout VSS; electrical VSS;
    inout VDD; electrical VDD;
    parameter integer data_pattern[15:0]={0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0};
    real val[15:0];


    analog begin
    $display(“%b ",data_pattern[0]);
    generate i(15,0)
    begin
    val[i]=data_pattern[i]*0;
    end
    generate j(15,0) begin
    V(DATA[j])<+val[j];
    end
    end
    endmodule

    • Post Points: 20
  • Mon, Jun 2 2014 10:19 PM

    Re: How to define a binary matrix parameter in Verilog A Reply

    Having tried it and now actually looked at the code, it's clear why it doesn't work. The line:

    val[i]=data_pattern[i]*0;

    Is the problem. It multiplies the value by 0, so it always outputs 0. With the *0 removed from this line (I removed the $display, because it wasn't terribly informative), and with this as a spectre netlist:

    //
    I1 (d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 VDD VSS) data_pattern_gen
    I2 (e15 e14 e13 e12 e11 e10 e9 e8 e7 e6 e5 e4 e3 e2 e1 e0 VDD VSS) data_pattern_gen data_pattern=[1,0,1,1,0,1,1,1,0,1,1,0,1,0,0,1]
    VDD (VDD 0) vsource dc=2
    VSS (VSS 0) vsource dc=0

    ahdl_include "data_pattern_gen.va"

    tran tran stop=1u

    I get the attached waveforms (I used transient primarily so I could add a marker to show the y values in the legend).

    Regards,

    Andrew.


    • Post Points: 20
  • Tue, Jun 3 2014 8:00 PM

    Re: How to define a binary matrix parameter in Verilog A Reply

    Hi Andrew,

    Thank you again for your help! The reason I added the line

        val[i]=data_pattern[i]*0;

    is to get my simulation runing, what I intend to do is making

        val[i]=data_pattern[i]*V(VDD);

    however, the data_pattern[0] in my simulation returns to be 01111111111111111111111111111111, this gives non-convergence error(voltage too high!).

    I made a screenshot, may be that gives more clear of my problem. Thank you in advance!


    • Post Points: 20
  • Wed, Jun 4 2014 2:00 AM

    Re: How to define a binary matrix parameter in Verilog A Reply

    It doesn't for me. What version of the simulator are you using? The version number should show at the top of the spectre.out log file when simulating (please give the complete number, including subversions).

    Andrew.

    • Post Points: 20
  • Wed, Jun 4 2014 2:29 AM

    Re: How to define a binary matrix parameter in Verilog A Reply

    Thank you Andrew, here is the heading of my spectre.out .

    Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator Version 10.1.1.441.isr25 32bit 25 Jul 2012 Copyright (C) 1989-2012 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc.

     Protected by U.S. Patents: 5,610,847; 5,790,436; 5,812,431; 5,859,785; 5,949,992; 5,987,238; 6,088,523; 6,101,323; 6,151,698; 6,181,754; 6,260,176; 6,278,964; 6,349,272; 6,374,390; 6,493,849; 6,504,885; 6,618,837; 6,636,839; 6,778,025; 6,832,358; 6,851,097; 6,928,626; 7,024,652; 7,035,782; 7,085,700; 7,143,021; 7,493,240; 7,571,401.


    Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. User: yangli Host: ccl HostID: 7F0100

    PID: 3300 Memory available: 99.8917 GB physical: 151.9494 GB CPU Type: Intel(R) Xeon(R) CPU E5-2690 0 O. 2.90GHz Processor PhysicallD CoreID Frequency
    0 0 0 2900.1 1 1 0 2900.1 2 0 1 2900.1 3 1 1 2900.1 4 0 2 2900.1 5 1 2 2900.1 6 0 3 2900.1 7 1 3 2900.1 8 0 4 2900.1 9 1 4 2900.1 10 0 5 2900.1 11 1 5 2900.1 12 0 6 2900.1 13 1 6 2900.1 14 0 7 2900.1 15 1 7 2900.1


    Simulating 'input.scs' on ccl at 5:18:22 PM, Wed Jun 4, 2014 (process id: 3300).

     Command line: /cadtools/cadence/MMSIM101/tools.lnx86/spectre/bin/32bit/spectre \ -env artist5.1.0 +escchars +log ../psf/spectre.out +inter=mpsc \ +mpssession=spectre5_7560_62 -format sst2 -raw \ -I/cadtools/pdk/towerjazz/cis018/HOTCODE/models/v4.51/spectre \ +lqtimeout 900 -many 5 -main 5 input.scs spectre pid = 3300 Loading /cadtools/cadence/MMSIM101/tools.lnx86/cmi/lib/5.0/libinfineon_sh.so Loading /cadtools/cadence/MMSIM101/tools.lnx86/cmi/lib/5.0/libphilips_sh.so Loading /cadtools/cadence/MMSIM101/tools.lnx86/cmi/lib/5.0/libsparam_sh.so Loading /cadtools/cadence/MMSIM101/tools.lnx86/cmi/lib/5.0/libstmodels_sh.so Time for NDB Parsing: CPU = 263.959 ms, elapsed = 287.039 ms. Time accumulated: CPU = 263.959 ms, elapsed = 287.039 ms. Peak resident memory used = 27.1 Mbytes.

    • Post Points: 5
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Started by microstudent at 30 May 2014 12:33 AM. Topic has 6 replies.