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 LEC mismatch b/w RTL and Lec-Friendly netlist 

Last post Fri, May 23 2014 11:36 AM by anudeep. 0 replies.
Started by anudeep 23 May 2014 11:36 AM. Topic has 0 replies and 2845 views
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  • Fri, May 23 2014 11:36 AM

    • anudeep
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    • Joined on Tue, Mar 18 2014
    • Posts 2
    • Points 10
    LEC mismatch b/w RTL and Lec-Friendly netlist Reply

    Hi,

         I am having the following issue and I am not been able to figure out the root cause for this issue.

         I am having a mixed design in which some portion of the design is RTL and some portion of the design is Netlist.

       I have done synthesis of this design and generated a lec friendly netlist(write_hdl -lec)

       I have done Lec b/w the lec-friendly netlist and the mixed design in both flat and hierarchical ways.

       The hierarchical comparision passed and the flat comparision is showing mismatches related to chipware components.

        Any idea on why this is happening?

        Is it required to do both flat and hierarchical comparision in this case?

       Awaiting for a sooner reply.

        Thank you all 

    • Post Points: 5
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Started by anudeep at 23 May 2014 11:36 AM. Topic has 0 replies.