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 Abstract Generator : ERROR (ABS-263): The routing direction for layer M1 is specified but no pitch value is present in the technology file 

Last post Mon, Apr 28 2014 5:27 AM by samung. 3 replies.
Started by samung 28 Apr 2014 03:33 AM. Topic has 3 replies and 295 views
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  • Mon, Apr 28 2014 3:33 AM

    • samung
    • Top 150 Contributor
    • Joined on Fri, Jun 14 2013
    • Posts 53
    • Points 625
    Abstract Generator : ERROR (ABS-263): The routing direction for layer M1 is specified but no pitch value is present in the technology file Reply
    Hello,
     
    this message comes after some other resolution messages (http://www.cadence.com/community/forums/T/29198.aspx).
     
    I am using the Abstract Generator tool to generate from a layout.oa a LEF view (and before that an abstract view).
     
    I found that my cadence tech file was not up to date (so I made and surely I still have to make some modifications inside). 
     
     
    With the following tech file, I have the ERROR     (ABS-263): The routing direction for layer M1 is specified but no pitch value is present in the technology file.
     
    There is no documentation regarding this error in  xxx//cadence/IC615/tools/cdnshelp/bin/cdnshelp
     
     
    Can someone please provide me the right definition for this pitch metal error ?
     
     
    Extract of the tech file: 

    ;********************************
    ; LAYER RULES
    ;********************************
    layerRules(

     equivalentLayers(
     ;( list of layers )
     ;( -------------- )
      ( ("PO" "drawing") ("PO" "tile") ("PO" "tile_O") ("PO" "filltr") ("PO" "mask") )
      ( ("M1" "drawing") ("M1" "tile") ("M1" "tile_O") )
      ( ("M2X" "drawing") ("M2X" "tile") ("M2X" "tile_O") ("M2X" "connector") )
      ( ("M3X" "drawing") ("M3X" "tile") ("M3X" "tile_O") ("M3X" "connector") )
      ( ("M4X" "drawing") ("M4X" "tile") ("M4X" "tile_O") ("M4X" "connector") )
      ( ("M5X" "drawing") ("M5X" "tile") ("M5X" "tile_O") ("M5X" "connector") )
      ( ("M6Z" "drawing") ("M6Z" "tile") ("M6Z" "connector") )
      ( ("M7Z" "drawing") ("M7Z" "tile") ("M7Z" "connector") )
      ( ("AP" "drawing") ("AP" "tile") ("AP" "connector") )
     ) ;equivalentLayers

    functions(
     ;( layer                       function        [maskNumber])
     ;( -----                       --------        ------------)
      ( DNW                       "nwell"     0            )
      ( NW                       "nwell"     1            )
      ( OD                       "diff"       2            )
      ( DCO                       "nplus"     3            )
      ( PO                       "poly"       4            )
      ( VTH_N                     "nplus"     5            )
      ( VTL_N                     "nplus"     6            )
      ( NP                       "nplus"     7            )
      ( VTH_P                     "pplus"     8            )
      ( VTL_P                     "pplus"     9            )
      ( PP                       "pplus"     10           )
      ( CO                       "cut"       11           )
      ( M1                       "metal"     12           )
      ( VIA1X                     "cut"       13           )
      ( M2X                       "metal"     14           )
      ( VIA2X                     "cut"       15           )
      ( M3X                       "metal"     16           )
      ( VIA3X                     "cut"       17           )
      ( M4X                       "metal"     18           )
      ( VIA4X                     "cut"       19           )
      ( M5X                       "metal"     20           )
      ( VIA5Z                     "cut"       21           )
      ( M6Z                       "metal"     22           )
      ( VIA6Z                     "cut"       23           )
      ( M7Z                       "metal"     24           )
      ( CB                       "cut"       29           )
      ( AP                       "metal"     30           )
      ( CB2                       "cut"       31           )
      ( FI                       "metal"     32           )
     ) ;functions

     routingDirections(
     ;( layer                       direction     )
     ;( -----                       ---------     )
      ( PO                       "none"       )
      ( M1                       "horizontal" )
      ( M2X                       "vertical"   )
      ( M3X                       "horizontal" )
      ( M4X                       "vertical"   )
      ( M5X                       "horizontal" )
      ( AP                       "vertical"   )
      ( M6Z                       "vertical"   )
      ( M7Z                       "horizontal" )
     ) ;routingDirections

    ) ;layerRules


    ...


    ;********************************
    ; CONSTRAINT GROUPS
    ;********************************
    constraintGroups(

     ;( group [override] )
     ;( ----- ---------- )
      ( "LEFDefaultRouteSpec" nil    "LEFDefaultRouteSpec"

        interconnect(
         ( validLayers   (AP  CB  M7Z  VIA6Z  M6Z  VIA5Z  M5X  VIA4X  M4X  VIA3X  M3X  VIA2X  M2X  VIA1X  M1  CO  PO  ) )
         ( validVias     (M1_NW  M1__NW  M2X_M1_via  M2X_M1_V_via  M3X_M2X_via  M3X_M2X_H_via  M4X_M3X_via  M4X_M3X_V_via  M5X_M4X_via  M5X_M4X_H_via  M6Z_M5X_via  M6Z_M5X_V_via  M7Z_M6Z_via  M7Z_M6Z_H_via  AP_M7Z_via  M1_POLYP  M1_POLYN  PTAP  NTAP  M1_POD  M1_NOD  M1__PO  M1__PO_H  M1_OD  M1_PO  M1_PO_H  M2X_M1  M2X_M1_V  M3X_M2X  M3X_M2X_H  M4X_M3X  M4X_M3X_V  M5X_M4X  M5X_M4X_H  M6Z_M5X  M6Z_M5X_V  M7Z_M6Z  M7Z_M6Z_H  AP_M7Z  FI_AP  ) )
        ) ;interconnect
      ) ;LEFDefaultRouteSpec

     ;( group [override] )
     ;( ----- ---------- )
      ( "virtuosoDefaultExtractorSetup" nil

        interconnect(
         ( validLayers  ( ( AP  drawing) ( AP  tile) ( AP  net) ( AP  pin) ( CB  drawing) ( CB  pin) ( CB  net) ( M7Z  drawing) ( M7Z  tile) ( M7Z  pin) ( M7Z  net) ( VIA6Z  drawing) ( VIA6Z  net) ( VIA6Z  pin) ( M6Z  drawing) ( M6Z  tile) ( M6Z  pin) ( M6Z  net) ( VIA5Z  drawing) ( VIA5Z  pin) ( VIA5Z  net) ( M5X  drawing) ( M5X  tile) ( M5X  tile_O) ( M5X  pin) ( M5X  net) ( VIA4X  drawing) ( VIA4X  pin) ( VIA4X  net) ( M4X  drawing) ( M4X  tile) ( M4X  tile_O) ( M4X  pin) ( M4X  net) ( VIA3X  drawing) ( VIA3X  pin) ( VIA3X  net) ( M3X  drawing) ( M3X  tile) ( M3X  tile_O) ( M3X  pin) ( M3X  net) ( VIA2X  drawing) ( VIA2X  pin) ( VIA2X  net) ( M2X  drawing) ( M2X  tile) ( M2X  tile_O) ( M2X  pin) ( M2X  net) ( VIA1X  drawing) ( VIA1X  pin) ( VIA1X  net) ( M1  drawing) ( M1  tile) ( M1  tile_O) ( M1  pin) ( M1  net) ( CO  drawing) ( CO  net) ( CO  pin) ( PO  drawing) ( PO  tile) ( PO  tile_O) ( PO  filltr) ( PO  net) ( PO  pin) ( OD  drawing) ( OD  tile) ( OD  tile_O) ( OD  filltr) ( OD  net) ( OD  pin) PP  NP  ( NW  drawing) ( NW  net) ( NW  pin) CutOxideWithPoly  CutSubWithNwell  d_pwell  ) )
         ( validVias     (M1_NW  M1__NW  M2X_M1_via  M2X_M1_V_via  M3X_M2X_via  M3X_M2X_H_via  M4X_M3X_via  M4X_M3X_V_via  M5X_M4X_via  M5X_M4X_H_via  M6Z_M5X_via  M6Z_M5X_V_via  M7Z_M6Z_via  M7Z_M6Z_H_via  AP_M7Z_via  M1_POLYP  M1_POLYN  PTAP  NTAP  M1_POD  M1_NOD  M1__PO  M1__PO_H  M1_OD  M1_PO  M1_PO_H  M2X_M1  M2X_M1_V  M3X_M2X  M3X_M2X_H  M4X_M3X  M4X_M3X_V  M5X_M4X  M5X_M4X_H  M6Z_M5X  M6Z_M5X_V  M7Z_M6Z  M7Z_M6Z_H  AP_M7Z  FI_AP  ) )
         ( errorLayer    noOverlapLayer1 )
        ) ;interconnect
      ) ;virtuosoDefaultExtractorSetup

     ;( group [override] )
     ;( ----- ---------- )
      ( "virtuosoDefaultSetup" nil

        interconnect(
         ( validLayers   (M1  M2X  M3X  M4X  M5X  M6Z  M7Z  AP  ) )
         ( validVias     (M1_POLYP  M1_POLYN  PTAP  NTAP  M1_POD  M1_NOD  M1__PO  M1__PO_H  M1_OD  M1_PO  M1_PO_H  M2X_M1  M2X_M1_V  M3X_M2X  M3X_M2X_H  M4X_M3X  M4X_M3X_V  M5X_M4X  M5X_M4X_H  M6Z_M5X  M6Z_M5X_V  M7Z_M6Z  M7Z_M6Z_H  AP_M7Z  FI_AP  ) )
        ) ;interconnect

        routingGrids(
         ( verticalPitch              "M1"   0.14 )
         ( horizontalPitch            "M1"   0.14 )
         ( verticalOffset             "M1"   0.0 )
         ( horizontalOffset           "M1"   0.0 )
         ( verticalPitch              "M2X"   0.18 )
         ( horizontalPitch            "M2X"   0.18 )
         ( horizontalOffset           "M2X"   0.0 )
         ( verticalOffset             "M2X"   0.0 )
         ( verticalPitch              "M3X"   0.14 )



    When I load the library and tech file with the Abstract Generator Tool, I have :

    INFO      (ABS-127): Attaching the cmos045_tech_abstract technology library to the library_test_place_route_lef library.
    LOG       (ABS-212): Verifying Technology Data...
    ERROR     (ABS-263): The routing direction for layer M1 is specified but no pitch value is present in the technology file.
    INFO      (ABS-232): Layer summary: 8 metal layer(s), 9 via layer(s), 3 poly layer(s), and 8 diff layer(s) found
    INFO      (ABS-234): Via summary: 40 valid via(s) found
     
     
     
    Thanks for any help !!
     
    P. 
    • Post Points: 20
  • Mon, Apr 28 2014 3:50 AM

    • ColinSutlieff
    • Top 500 Contributor
    • Joined on Tue, Apr 21 2009
    • Feldkirchen, Bavaria
    • Posts 35
    • Points 700
    Re: Abstract Generator : ERROR (ABS-263): The routing direction for layer M1 is specified but no pitch value is present in the technology file Reply

     Hi Samung,

     

    2 possibilities here.

     

    1.  The technology that contains the above information is not actually in your technology graph.

     You don't specify if the libraries " cmos045_tech_abstract" or "library_test_place_route_lef" contain this information.

    I suspect it should be in another library that you have not mentioned.

     

    2. This is probably the real reason:

    When you use the abstract Generator, with default settings. It looks for information in the "LEFDefaultRouteSpec" constraint Group.

    You have not defined it there.

    But you do have it defined in anothe C.G: "virtuosoDefaultSetup".

    So there are 2 alternatives:

    1.Put the routing grids information in the LefDefaultRouteSpec CG.

    or

    2. In the abstract generator click  File->General options->  and enter "virtuosoDefaultSetup".

    That should fix the problem

     

    Colin

    • Post Points: 35
  • Mon, Apr 28 2014 5:27 AM

    • samung
    • Top 150 Contributor
    • Joined on Fri, Jun 14 2013
    • Posts 53
    • Points 625
    Re: Abstract Generator : ERROR (ABS-263): The routing direction for layer M1 is specified but no pitch value is present in the technology file Reply

    Thanks Colin, it works defining the routingGrids in the "LEFDefaultRouteSpec" group.

     

    tech file :

    ;********************************

    ; CONSTRAINT GROUPS

    ;********************************

    constraintGroups(

     

     ;( group [override] )

     ;( ----- ---------- )

      ( "LEFDefaultRouteSpec" nil    "LEFDefaultRouteSpec"

     

        interconnect(

         ( validLayers   (AP  CB  M7Z  VIA6Z  M6Z  VIA5Z  M5X  VIA4X  M4X  VIA3X  M3X  VIA2X  M2X  VIA1X  M1  CO  PO  ) )

         ( validVias     (M1_NW  M1__NW  M2X_M1_via  M2X_M1_V_via  M3X_M2X_via  M3X_M2X_H_via  M4X_M3X_via  M4X_M3X_V_via  M5X_M4X_via  M5X_M4X_H_via  M6Z_M5X_via  M6Z_M5X_V_via  M7Z_M6Z_via  M7Z_M6Z_H_via  AP_M7Z_via  M1_POLYP  M1_POLYN  PTAP  NTAP  M1_POD  M1_NOD  M1__PO  M1__PO_H  M1_OD  M1_PO  M1_PO_H  M2X_M1  M2X_M1_V  M3X_M2X  M3X_M2X_H  M4X_M3X  M4X_M3X_V  M5X_M4X  M5X_M4X_H  M6Z_M5X  M6Z_M5X_V  M7Z_M6Z  M7Z_M6Z_H  AP_M7Z  FI_AP  ) )

        ) ;interconnect

     

        routingGrids(

         ( verticalPitch              "M1"   0.14 )

         ( horizontalPitch            "M1"   0.14 )

         ( horizontalOffset           "M1"   0.0 )

         ( verticalOffset             "M1"   0.0 )

         ( verticalPitch              "M2X"   0.18 )

         ( horizontalPitch            "M2X"   0.18 )

         ( horizontalOffset           "M2X"   0.0 )

         ( verticalOffset             "M2X"   0.0 )

         ( verticalPitch              "M3X"   0.14 )

         ( horizontalPitch            "M3X"   0.14 )

         ( horizontalOffset           "M3X"   0.0 )

         ( verticalOffset             "M3X"   0.0 )

         ( verticalPitch              "M4X"   0.14 )

         ( horizontalPitch            "M4X"   0.14 )

         ( horizontalOffset           "M4X"   0.0 )

         ( verticalOffset             "M4X"   0.0 )

         ( verticalPitch              "M5X"   0.14 )

         ( horizontalPitch            "M5X"   0.14 )

         ( horizontalOffset           "M5X"   0.0 )

         ( verticalOffset             "M5X"   0.0 )

         ( verticalPitch              "M6Z"   0.84 )

         ( horizontalPitch            "M6Z"   0.84 )

         ( horizontalOffset           "M6Z"   0.0 )

         ( verticalOffset             "M6Z"   0.0 )

         ( verticalPitch              "M7Z"   0.84 )

         ( horizontalPitch            "M7Z"   0.84 )

         ( horizontalOffset           "M7Z"   0.0 )

         ( verticalOffset             "M7Z"   0.0 )

         ( verticalPitch              "AP"   5.0 )

         ( horizontalPitch            "AP"   5.0 )

         ( horizontalOffset           "AP"   0.0 )

         ( verticalOffset             "AP"   0.0 )

        ) ;routingGrids

     

      ) ;LEFDefaultRouteSpec

     

    Abstract generator Log :

    INFO      (ABS-127): Attaching the cmos045_tech_abstract technology library to the library_test_place_route_lef library.

    LOG       (ABS-212): Verifying Technology Data...

    INFO      (ABS-232): Layer summary: 8 metal layer(s), 9 via layer(s), 3 poly layer(s), and 8 diff layer(s) found

    INFO      (ABS-234): Via summary: 40 valid via(s) found

    • Post Points: 5
  • Mon, Apr 28 2014 5:27 AM

    • samung
    • Top 150 Contributor
    • Joined on Fri, Jun 14 2013
    • Posts 53
    • Points 625
    Re: Abstract Generator : ERROR (ABS-263): The routing direction for layer M1 is specified but no pitch value is present in the technology file Reply

    Thanks Colin, it works defining the routingGrids in the "LEFDefaultRouteSpec" group.

     

    tech file :

    ;********************************

    ; CONSTRAINT GROUPS

    ;********************************

    constraintGroups(

     

     ;( group [override] )

     ;( ----- ---------- )

      ( "LEFDefaultRouteSpec" nil    "LEFDefaultRouteSpec"

     

        interconnect(

         ( validLayers   (AP  CB  M7Z  VIA6Z  M6Z  VIA5Z  M5X  VIA4X  M4X  VIA3X  M3X  VIA2X  M2X  VIA1X  M1  CO  PO  ) )

         ( validVias     (M1_NW  M1__NW  M2X_M1_via  M2X_M1_V_via  M3X_M2X_via  M3X_M2X_H_via  M4X_M3X_via  M4X_M3X_V_via  M5X_M4X_via  M5X_M4X_H_via  M6Z_M5X_via  M6Z_M5X_V_via  M7Z_M6Z_via  M7Z_M6Z_H_via  AP_M7Z_via  M1_POLYP  M1_POLYN  PTAP  NTAP  M1_POD  M1_NOD  M1__PO  M1__PO_H  M1_OD  M1_PO  M1_PO_H  M2X_M1  M2X_M1_V  M3X_M2X  M3X_M2X_H  M4X_M3X  M4X_M3X_V  M5X_M4X  M5X_M4X_H  M6Z_M5X  M6Z_M5X_V  M7Z_M6Z  M7Z_M6Z_H  AP_M7Z  FI_AP  ) )

        ) ;interconnect

     

        routingGrids(

         ( verticalPitch              "M1"   0.14 )

         ( horizontalPitch            "M1"   0.14 )

         ( horizontalOffset           "M1"   0.0 )

         ( verticalOffset             "M1"   0.0 )

         ( verticalPitch              "M2X"   0.18 )

         ( horizontalPitch            "M2X"   0.18 )

         ( horizontalOffset           "M2X"   0.0 )

         ( verticalOffset             "M2X"   0.0 )

         ( verticalPitch              "M3X"   0.14 )

         ( horizontalPitch            "M3X"   0.14 )

         ( horizontalOffset           "M3X"   0.0 )

         ( verticalOffset             "M3X"   0.0 )

         ( verticalPitch              "M4X"   0.14 )

         ( horizontalPitch            "M4X"   0.14 )

         ( horizontalOffset           "M4X"   0.0 )

         ( verticalOffset             "M4X"   0.0 )

         ( verticalPitch              "M5X"   0.14 )

         ( horizontalPitch            "M5X"   0.14 )

         ( horizontalOffset           "M5X"   0.0 )

         ( verticalOffset             "M5X"   0.0 )

         ( verticalPitch              "M6Z"   0.84 )

         ( horizontalPitch            "M6Z"   0.84 )

         ( horizontalOffset           "M6Z"   0.0 )

         ( verticalOffset             "M6Z"   0.0 )

         ( verticalPitch              "M7Z"   0.84 )

         ( horizontalPitch            "M7Z"   0.84 )

         ( horizontalOffset           "M7Z"   0.0 )

         ( verticalOffset             "M7Z"   0.0 )

         ( verticalPitch              "AP"   5.0 )

         ( horizontalPitch            "AP"   5.0 )

         ( horizontalOffset           "AP"   0.0 )

         ( verticalOffset             "AP"   0.0 )

        ) ;routingGrids

     

      ) ;LEFDefaultRouteSpec

     

    Abstract generator Log :

    INFO      (ABS-127): Attaching the cmos045_tech_abstract technology library to the library_test_place_route_lef library.

    LOG       (ABS-212): Verifying Technology Data...

    INFO      (ABS-232): Layer summary: 8 metal layer(s), 9 via layer(s), 3 poly layer(s), and 8 diff layer(s) found

    INFO      (ABS-234): Via summary: 40 valid via(s) found

    • Post Points: 5
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Started by samung at 28 Apr 2014 03:33 AM. Topic has 3 replies.