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# Weird PAC simulation results

Last post Tue, Feb 26 2008 11:43 PM by archive. 3 replies.
 Started by archive 26 Feb 2008 11:43 PM. Topic has 3 replies and 1351 views
• #### Tue, Feb 26 2008 11:43 PM

• archive
• Joined on Fri, Jul 4 2008
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Weird PAC simulation results
 Recently I encountered some problems with PAC simulations so I decided to test the PAC simulation. I built the simple RC circuit with the R replaced by a switched-capacitor CR as shown in the following figure: Vin -------(phi 1) -------(phi 2) ----------Vout | | ------ ------ CR | | ------ gnd phi1 and phi2 are non-overlapping clocks controlling two NMOS switches respectively. Vout is connected to the ground (gnd) through another capacitor (not shown). To verify the simulation issues, I constructed three similar circuits as follows (all with same input Vin and clock signals): Circuit (1): NMOS model set 1, Vout = vosci Circuit (2): NMOS model set 2, Vout = vosc Circuit (3): Switched capacitor CR is replaced by its equivalent resistor R, Vout = vorc. PSS simulations are similar for vosci and vosc while vorc is simply a dc voltage as expected. However, when proceeding to perform the PAC simulation, I obtained the following results (see attached). From the graphs, it can be seen that vosci (Circuit 1) and vorc are as expected from simple RC circuit but vosc (Circuit 2) is very odd with a gain of below -100dB. As the only difference between Circuit (1) and Circuit (2) is the NMOS model (BSIM3), could anyone help me solve the weird PAC results mystery? Thanks! Originally posted in cdnusers.org by harmonics pacsim.pdf
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• #### Wed, Feb 27 2008 9:01 AM

• archive
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RE: Weird PAC simulation results
 Very hard to tell without seeing your circuit and models (or at least the netlist and models to see what your analysis statements is). Your ASCII art schematic got scrambled, so it's very hard to tell.Probably the best idea is to contact Cadence customer support, and then work with us to reproduce it. Often these problems are simply explained or solved, but in this case it's hard to do so without seeing your setup.Regards,Andrew.Originally posted in cdnusers.org by adbeckett
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• #### Thu, Feb 28 2008 12:25 AM

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RE: Weird PAC simulation results
 Hi Andrew, Thanks for replying. I hereby attach the schematic. BTW, the NMOS model in Circuit 1 is based on BSIM3 version 3.2 and that in Circuit 2 is based on BSIM3 version 3.3. Could it be due to some missing or undefined parameters in BSIM3 version 3.3?Originally posted in cdnusers.org by harmonics pacct.jpg
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• #### Fri, Feb 29 2008 3:39 AM

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RE: Weird PAC simulation results
 Thanks, but that doesn't really tell me anything I didn't already know. I doubt it's the models - more likely to be the testbench or simulation setup.Also, you've only shown me the circuit, and not the testbench, or the analysis setup, or the models. There are an awful lot more variables where something could be wrong with the setup.That's why I suggested going to customer support (sourcelink.cadence.com) - we (Cadence) can then work with you to understand fully the problem, reproduce it, and hopefully correct what's not right with the setup (or fix the tool if something really is wrong with it).Regards,Andrew.Originally posted in cdnusers.org by adbeckett
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