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 initial condition in spectre verilog simulator 

Last post Sat, Jan 19 2008 11:10 AM by archive. 2 replies.
Started by archive 19 Jan 2008 11:10 AM. Topic has 2 replies.
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  • Sat, Jan 19 2008 11:10 AM

    • archive
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    initial condition in spectre verilog simulator Reply

    hi

    I have a memory design which is 32X32 cell in size and i need to initialize each cell to a value. i.e. around 2048 (1024 bit +1024 bitbar) nodes.

    So is there any way other than using Simulation>converegnce aid > initial condition in the analog environment, like using a script or something else which makes the job easier.

    thanks,
    Siddharth


    Originally posted in cdnusers.org by siddharth
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  • Mon, Jan 21 2008 1:33 AM

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    RE: initial condition in spectre verilog simulator Reply

    You can create an include file using the "ic" statement (see "spectre -h ic") and then reference this through the Setup->Model Libraries form in ADE.

    Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett
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  • Tue, Jan 22 2008 12:30 AM

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    RE: initial condition in spectre verilog simulator Reply

    thank you ....


    Originally posted in cdnusers.org by siddharth
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Started by archive at 19 Jan 2008 11:10 AM. Topic has 2 replies.