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 Can someone help me figure out where does power analysis of Cadence Encounter RTL Compiler comes from 

Last post Thu, Mar 20 2014 10:51 PM by ajay01. 7 replies.
Started by Haoxiang 06 Mar 2014 01:06 PM. Topic has 7 replies and 1729 views
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  • Thu, Mar 6 2014 1:06 PM

    • Haoxiang
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    Can someone help me figure out where does power analysis of Cadence Encounter RTL Compiler comes from Reply

    Hi all,

     New to this area, I have two questions that need your help. 

    1st, when I get the power analysis from Cadence Encounter RTL Compiler, It automatically shows Leakage, Internal, Net and Switching Power of the generated schematic. But then I get comfused, under which input pattern does the Compiler infer all the power values, especially switching power, since it's directly related to the frequency of input?

     2nd, what's the difference between Leakage Power and Internal Power? And does Net Power means power consumed from the interconnect? I get confusion about these terms

     Thank you very much for your notice and help!

    Best 

    • Post Points: 20
  • Wed, Mar 12 2014 12:14 AM

    • ajay01
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    Re: Can someone help me figure out where does power analysis of Cadence Encounter RTL Compiler comes from Reply

     1.Generaly basic power information come from .lib .like how much leakage when cell have different-different logic.for each cell in stander cell lib. and other information come from collapsed/port view of standered cell and macro.

    2.Two type of power in CMOS :

    a.dynamic power(switching power)

    b.static power(internal power)

    And leakage power is leakge of both dynamic and static IR drop.

     For detail of CMOS power:

    http://en.wikipedia.org/wiki/CMOS#Power:_switching_and_leakage

    Thanks,

    Ajay

    • Post Points: 35
  • Mon, Mar 17 2014 9:37 AM

    • Haoxiang
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    Re: Can someone help me figure out where does power analysis of Cadence Encounter RTL Compiler comes from Reply
    Thank you for your answer, it helps a lot. Got two more questions that you may can help me with.

    1. How do you mean by leakage of dynamic power? Is that equivalent to short-circuit power?

    2. And what's Net Power that I mentioned in my question? Does net power have something in common with the static IR drop you mentioned? Does Net Power includes Ldi/dt voltage drop?

    Thank you again for your quick response

    Best,
    Haoxiang
    • Post Points: 20
  • Wed, Mar 19 2014 4:38 AM

    • ajay01
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    Re: Can someone help me figure out where does power analysis of Cadence Encounter RTL Compiler comes from Reply

     Hi Haoxiang,

    1.leakge of dynamic power is not only short circuit power but it is also calculating ir drop during Charging and discharging of load capacitances.

    so  dynamic power leakage= short circuit power+ power dissipation during Charging and discharging of load capacitances.

    2.Yes net power related to static IR drop.its independent of switching activity means dynamic power.

    • Post Points: 5
  • Wed, Mar 19 2014 12:06 PM

    • zhaojun
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    Re: Can someone help me figure out where does power analysis of Cadence Encounter RTL Compiler comes from Reply
    Hi Ajay, I have the same question with the power consumption results in RTL Compiler. I found your reply really helpful. But I still have 2 further questions about it: 1. As to the dynamic power, how does the RTL Compiler define the working frequency? 2. About the leakage power, what's the file in the standard cell library that defines it in different situations? Looking forward to your reply! Thank you very much! Best, Zhaojun
    • Post Points: 20
  • Wed, Mar 19 2014 11:29 PM

    • ajay01
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    Re: Can someone help me figure out where does power analysis of Cadence Encounter RTL Compiler comes from Reply

    Hi ,

    1.As i mentioned,
    Dynamic power is the sum of two factors: switching power plus short-circuit power.
    Switching power is dissipated when charging or discharging internal and net
    capacitances. Short-circuit power is the power dissipated by an instantaneous shortcircuit
    connection between the supply voltage and the ground at the time the gate
    switches state.
    Pswitching = a .f.Ceff .Vdd2
    Where a = switching activity, f = switching frequency, Ceff = effective capacitance,
    Vdd = supply voltage
    Pshort-circuit = Isc .Vdd.f
    Where Isc = short-circuit current during switching, Vdd = supply voltage,
    f = switching frequency

    As we will go ahead in technology we required chip should work faster means frequency will increase.
    So as shown above equation dynamic IR drop increase.
    For that we are using Low Power Techniques and CPF flow.
    So RTL compiler set frequency based on requirement and leakage calculation and technicians which will be used during
    Physical implementation.

    2. In  standard cell library that defines as below:
    consider its a buffer.
    Then it will define leakage power when logic A and !A.
    And internal power At pin A.full table.
    Like that for all std. cell power define with different logic.

     

     

     

    • Post Points: 20
  • Thu, Mar 20 2014 11:06 AM

    • zhaojun
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    Re: Can someone help me figure out where does power analysis of Cadence Encounter RTL Compiler comes from Reply
    Hi Ajay, Thank you so much for your answers! I found it really helpful to understand the RTL Compiler. Then in order to satisfy different purposes like low power consumption, small area, etc. , are we able to change synthesis mode? I didn't find any CPF file in my rc directory, so in this case, what's the default synthesis frequency and input types?
    • Post Points: 20
  • Thu, Mar 20 2014 10:51 PM

    • ajay01
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    Re: Can someone help me figure out where does power analysis of Cadence Encounter RTL Compiler comes from Reply

     Hi ,

    I am working in physical design.so i dont have idea about synthesis mode and input type..

    If any fundamental question  then i can help you.

    Thanks,

    Ajay

     

    • Post Points: 5
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Started by Haoxiang at 06 Mar 2014 01:06 PM. Topic has 7 replies.