Go with what works best for your design flow. I have found that it is useful in many circumstances to make a separate symbol for each bank and include the VCC/GND for that bank in that block. More than 50-75 pins per block can be cumbersome on a schematic unless you have some grouped busses for example.
The first thing I do is convert the datasheet pinlist to a text file using Adobe or some PDF reader. In some circumstances the FPGA vendor will supply an Excel pinlist -- just ask.
Once you have the pinlist you can quickly use the OrCAD spreadsheet editor to place the pins in each block. You want to have heterogenous part selected and predetermine how many blocks you want. In the spreadsheet editor you can choose which block the pin goes and what type of pin it is (input, output, bidir, 3state).
Once the spreadsheet is completed you can review the symbols and move pins as required for better schematic connectivity.
Think about how to manage pinswapping in the future --- that is a very powerful and necessary feature of FPGAs. Read up on that.
Hope that starts you off.