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# Timing constraine problem in synthesis

Last post Thu, Feb 27 2014 7:12 AM by grasshopper. 1 replies.
 Started by KUMARJAYA 27 Feb 2014 05:56 AM. Topic has 1 replies and 827 views
• #### Thu, Feb 27 2014 5:56 AM

• KUMARJAYA
• Joined on Sat, Sep 14 2013
• Posts 4
• Points 65
Timing constraine problem in synthesis
 i had design a divider and a up/down counter for a section of my project.Input frequency of clock is 50mhz and it is divided by 50(1mhzclock) to clock up/down counter.but after synthesis their exist a timing problem to registers define for up/down countertiming problem isTHE FOLLOWING SEQUENTIAL CLOCK PIN HAVE NO CLOCK WAVEFORM DRIVING THEM.NO TIMING CONSTRAINE WILL BE DERIVED FOR PATH LEADING TO AND FROM THESE PINS(which is registers define in up/down counter)so how can i define clock(1mhz) to up/down counter(which is divided from input clock of 50mhz)?
• Post Points: 20
• #### Thu, Feb 27 2014 7:12 AM

• grasshopper
• Joined on Fri, Jul 18 2008
• Chelmsford, MA
• Posts 242
• Points 3,205
Re: Timing constraine problem in synthesis
 Hi Kumarjaya, the message seems quite clear in that the flop's clock is undefined and the clock waverform is infered. Sounds like you need a 'create_generate_clock' constraint on the output of your divider circuit gh-
• Post Points: 5