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 delay between 2 signals 

Last post Thu, Feb 27 2014 10:37 AM by grasshopper. 1 replies.
Started by vvgulyaev 25 Feb 2014 02:05 AM. Topic has 1 replies and 1763 views
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  • Tue, Feb 25 2014 2:05 AM

    • vvgulyaev
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    • Joined on Tue, Feb 25 2014
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    • Points 20
    delay between 2 signals Reply
    Hello, i am beginner rtl compiler user. I have a question about synthesis with rtl compiler.

    For example, i have 2 signals sig1 and sig2. In verilog code:

    assign #10 sig2=sig1;
    In synthesis I want to insert delay buffer between sig2 and sig1. Library which I want to use is contain delay buffer cells for different time delays. But i don't know which tcl command for rtl compiler inserts delay buffer between 2 signals.
    • Post Points: 20
  • Thu, Feb 27 2014 10:37 AM

    • grasshopper
    • Top 25 Contributor
    • Joined on Fri, Jul 18 2008
    • Chelmsford, MA
    • Posts 242
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    Re: delay between 2 signals Reply

    Verilog delay statement are not synthesizable and synthesis tools simply ignore them. Multiple ways swap a buffer for a delay cell so please check with your local AE.There is no verilog statement to ensure a buffer or delay cell is inserted short of hand-instantiating the delay cells

     gh-

    • Post Points: 5
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Started by vvgulyaev at 25 Feb 2014 02:05 AM. Topic has 1 replies.