Hello, i am beginner rtl compiler user. I have a question about synthesis with rtl compiler.
For example, i have 2 signals sig1 and sig2. In verilog code:
synthesis I want to insert delay buffer between sig2 and sig1. Library
which I want to use is contain delay buffer cells for different time
delays. But i don't know which tcl command for rtl compiler inserts
delay buffer between 2 signals.