Andrew, I checked, those cells are inside the CDL netlist. I am attaching the final exported from schematics netlist for LVS.
By the way, I noticed that there is already update available for my kit from foundry, I updated to the latest version of the kit, then I pulled up my basic inverter, exported its netlist, and DRC'ed and LVS'ed its layout, all worked! No errors!
But now, I again go to some template frame, which has bondpads and some esd cells/clamps. And again I get errors saying bondpad not defined! It does not make any sense!
Here is the output of LVS when it quits with error:
Reading schematic network
inputting netlist /media/cadence/runs/schematic/TOP_frame_template2/TOP_frame_template2.netlist.lvs
*WARNING* *.EQUATION is not supported
*WARNING* *.MEGA is not supported
*WARNING* *.PIN is not supported
*WARNING* The capability to discard or ignore devices is not available
Therefore all devices were included in the output
Even though no *.BIPOLAR command was found
Reading layout network
inputting network ./runs/LVS/TOP_frame_template2/TOP_frame_template2.ldb
*ERROR* cell 'pcdcap' is not defined.
*ERROR* cell 'bondpad' is not defined.
*WARNING* /home/soft/cadence/assura41/tools/assura/bin/nvn exit with bad status
*WARNING* Status 256
*WARNING* Assura execution terminated
*WARNING* An error occurred during Nvn PreExtraction.
LVS preprocessing requires a successful run of Nvn.
Assura will now terminate.
Any ideas where else should I look into? I am amazed that I even updated the whole kit, and successfully DRC/LVS'ed the inverter with transistors, but the design of some template pad frame with PADs and ESD cells gives me this error.
What else could go wrong?