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 Great Opportunities in EDA, ARP, Place and Route, Layout, Management and Logic Design 

Last post Tue, Feb 11 2014 6:38 PM by epeefencer. 0 replies.
Started by epeefencer 11 Feb 2014 06:38 PM. Topic has 0 replies and 557 views
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  • Tue, Feb 11 2014 6:38 PM

    • epeefencer
    • Not Ranked
    • Joined on Fri, Jan 31 2014
    • Posts 2
    • Points 10
    Great Opportunities in EDA, ARP, Place and Route, Layout, Management and Logic Design Reply

    I have been contacted with some outstanding new opportunities inside a large corporation that has a big presence in Silicon Valley, CA and Austin, TX. We are looking primarily for experts in ECAD, EDA, Place and Route, Layout, etc. There are approximately 30 positions open, which is a welcome sign of growth within the Technology job-market. These are opportunities with a dynamic and successful company that is a dedicated foundry, serving the global marketplace.   


    #1) Place & Route Technical Engineer/Manager

    Job Location: San Jose, California


    • ASIC block-level implementation and/or full-chip integration projects. 
    • Customer on-site APR support.



    • B.S. or above in EE or CS
    • 6+ years chip physical implementation experience
    • Fluent with major EDA tools/design flows
    • Experience with N40 or below technology
    • Experience in chip integration and signoff
    • Proven record in multi-million gate design production tapeouts
    • Experience in any of the following is a plus: 28nm technology
    • Low-power implementation methodology
    • Advanced timing methodology
    • Independently complete APR
    • Personal Attributes:  
    • Aggressive in learning and problem-solving
    • Good communication
    • Can work independently


    #2) Automated Place and Route Sr. Engineer and Technical Manager

    Job Location: Austin, Texas


    • Be responsible for advanced chip implementation flow development, chip PPA boost, and support headquarter advanced technology for 16/10 nm EDA router engagement.
    • Act as the customer solution provider with headquarter.


    • MS or PHD in CS, EE related field with experience in APR, physical verification, chip implementation, or CAD algorithm.



    #3) Place & Route - Sr. Engineers/Technical Managers

    Job Location:    San Jose, California


    Be responsible for ASIC integration/implementation projects, and advance design methodology build-up.


    • BS or above in EE/CS. For Sr. Engineer positions, must have 5-10+ years of related experience. For manager positions, 10~15+ years of chip physical implementation experience.
    • Be an expert in ASIC RTL-to-GDS design flow. Fluent with Synopsys/Cadence Synthesis/APR tools/flows. Skilled in Tcl/Perl utility program coding.
    • Experienced with 28nm and below technologies. Experienced in chip integration and signoff. Proven record in multi-million gate design production tapeouts. Innovative in PPA optimizations and APR design methodology.
    • Must be service driven and able to interface with customer on specs/signoff/job scope discussion. Must have good communication skills, and can take tapeout pressure and work independently.
    • Experienced in any of the following is a plus:
    • 20nm technology
    • Mobile application processor’s eCPU/eGPU implementation
    • Low-power implementation methodology
    • Application processor implementation                             


           #4) Layout Engineer/Sr. Layout Engineer
                                            Job Location: San Jose, California

    • Provide on-site support for customer’s layout projects for the most advanced technology.
    • Design complex layouts for every kind of circuits design.
    • Analyze floor plans and complex circuits with circuit designer.
    • Run complete set of design verification programs to complete the layout with zero errors goal.
    • Work with other layout and circuit designer to resolve any technical issues that will affect layout to ensure high quality.
    • Meet project objectives and milestones.
    • Train and mentor other new layout engineers
    • Provide support to HQ on IP/Libraries development.
    • Utilize design knowledge and co-work with RD, to evaluate and robust design rule.



    • A Bachelor's degree with 5+ years of experience of 65nm, 40nm, 28nm CMOS circuits used in Standard Cell or SRAM layout.
    • Basic understanding of semiconductor devices and process.
    • Excellent communication skills and able to work with different functional teams.
    • Bilingual in Mandarin a plus not requirement.


    #5) Timing Sr. Engineer / Technical Manager

    Job Location: Austin, Texas


    • Be responsible for EDA engagement on advance technology node timing accuracy, design test suites, golden data simulation.


    • PhD or MS in CS/EE related filed with the experiences below.
    • Familiar with STA tool Synopsys PrimeTime or Cadence ETS usage/setting.
    • Familiar with STD cell library liberty format.
    • Familiar with spice simulation.
    • Variation methodology: 
    • OCV methodology - traditional OCV , AOCV usage
    • Knowing the following would be a plus:
    • Timing closure techniques like performance push and hold time fixing
    • Cell-based delay calculation knowledge and delay/noise model


                             #6) Sr. Logic Design Engineer/ Manager

                                                Location: San Jose, California


    ·     Senior Logic Design Engineer responsible for architecting, implementing highly integrated and complex multifunctional SOC designs. 

    ·     Must have system view to architect, micro-architect, and system analysis on complicate SoC.

    ·     Understand, generate or enhance SOC platforms that could incorporate processor, graphics, memory and high speed IO.

    ·     Able to drive, manage and implement a complex Chip design from define the goals, requirements, execution plan, defining critical milestones, create the specification, RTL coding to Physical Chip implementation.

    ·      Able to do the system level debugging from high level, logic level to circuit level.

    ·      Write detailed specifications; perform static timing, logic synthesis, lab debug and design verification.

    ·      Work closely with circuit, physical design, verification, and software engineers to deliver logically correct and electrically robust designs.

    ·      May supervise the activities of others.



    ·         Education:

                  o   PhD and 7+ years’ experience

                  o   M.S./B.S. and 10+ years’ experience

    ·         Must have system level view and system debug experience.

    ·         Must have previous experience integrating processor with memory  

              subsystem, and high speed IO’s on a highly integrated SOC chip.

    ·         Mobile SoC experience is plus.

    ·         Must have prior experience working with tools for:

           o   Simulation: System Verilog, VCS/IUS

           o   Modeling: C++, Perl, System C

           o   Verification: SVA, System-C/Verilog

           o   Chip Design: RTL and Physical design tools

    ·        Act independently to determine methods and procedures on new or special assignments. 

    IF you are interested in exploring one or more of these opportunities to work with some of the leading technology companies in the world, please respond with a resume. Referrals, recommendations and suggestions are always welcome, as are 'random' resume submissions for other possible opportunities not described above.


                     Best Regards, 

                     Nicholas Meyler

                     GM/President, Technology

                     Wingate Dunross, Inc.

                     ph (818)597-3200 ext. 211

                     URL: www.wdsearch.com

                     Email: Nickm@wdsearch.com   

    • Post Points: 5
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Started by epeefencer at 11 Feb 2014 06:38 PM. Topic has 0 replies.