Home > Community > Forums > Functional Verification > initial statement issue in IFV

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 initial statement issue in IFV 

Last post Tue, Feb 11 2014 9:48 PM by DouglasYaya. 6 replies.
Started by DouglasYaya 07 Feb 2014 11:57 PM. Topic has 6 replies and 2389 views
Page 1 of 1 (7 items)
Sort Posts:
  • Fri, Feb 7 2014 11:57 PM

    initial statement issue in IFV Reply

    Dear Sir/Lady:

    I have a question while using IFV, there is a simulation model in my design, after running the verification flow for several cycles, I did not find PRINET was set to  1b'1, this seems to be the issue related with initial statement, I do not know how to slove, could you help me? Thank you!

      =========================Command Line=========================

     iev +64bit *.sv +tcl+sim.tcl +covoverwrite +coverage+all

     =========================simulation model=========================

     module PRI(PRI);
      input PRI;
    parameter RST_PULSE = 1;

    reg PRINET;

    initial
    begin
     PRINET = 1'b0;
     #RST_PULSE
     PRINET = 1'b1;
    end

    endmodule

    =========================TCL script file=========================

    clock -add  ck  -initial 1  -width 1  -period 2 


    force   sp  1'b1
    force   cd  1'b0
    force   d   1'b1

    run 6

    init -load -sst2 douglas.shm

    init -show

    constraint -add -pin sp 1'b1

    constraint -add -pin cd 1'b0

    constraint -add -pin d  1'b1

    assert -add -block

    assert -add -fsm

    define constraint_trace on

    define witness_check trace

    prove

     

    Filed under:
    • Post Points: 20
  • Mon, Feb 10 2014 7:14 AM

    • TAM1
    • Top 75 Contributor
    • Joined on Thu, Jul 17 2008
    • HOME, PA
    • Posts 83
    • Points 1,105
    Re: initial statement issue in IFV Reply

     IFV workd with a model built from the synthesized RTL design. Initial blocks are ignored by IFV because they are not part of the synthesized circuit. The workaround is to add the statements to your initialization sequence and constraints.

     

    force PRINET 0
    force resetn 0
    run 2
    const -add -pin resetn 1 -reset
    const -add -pin PRINET 1'b1

    • Post Points: 20
  • Mon, Feb 10 2014 9:46 PM

    Re: initial statement issue in IFV Reply

    Thank you TAM1, you save me again!

     BTW, if there is a large design with an initial blocks in some module, it would cause problems if the IFV engineer does not know this, right? If so, how to avoid this risk?

    Douglas

    02/11/2014

    • Post Points: 20
  • Tue, Feb 11 2014 5:43 AM

    • TAM1
    • Top 75 Contributor
    • Joined on Thu, Jul 17 2008
    • HOME, PA
    • Posts 83
    • Points 1,105
    Re: initial statement issue in IFV Reply

     No one should design hardware that depends on an initial block to work correctly. Initial blocks in design RTL are often forbidden by design methodologies for just this reason.

    • Post Points: 20
  • Tue, Feb 11 2014 5:14 PM

    Re: initial statement issue in IFV Reply

     Yes, I totally agree with you, based on this, if I want to verify a design with some simulation modles(e.g., DDR momory, PCI slave device), it's impractical to apply the IFV to the whole testbench? since these simulation modles may have some unsynthesizable statements. Do you mean that I still need to use the "irun"?

     

    Much thanks,

    Douglas

    • Post Points: 20
  • Tue, Feb 11 2014 6:21 PM

    • TAM1
    • Top 75 Contributor
    • Joined on Thu, Jul 17 2008
    • HOME, PA
    • Posts 83
    • Points 1,105
    Re: initial statement issue in IFV Reply

    One applies the formal tool to the DUT itself. There should be no testbench involved. IFV applies all possible stimulus to the design (subject to the constraints), so no testbench should be involved. 

     

    If IFV finds that parts of the design itself are not synthesizable, it will complain loudly and "black-box" them. That means it will drop them from the analysis and make no assumptions about their outputs. 

     

    If you want to analyze a block that communicates to a memory or across a particular protocol, then things get more complex. You don't necessarily need a fully synthesizable model of the connected block. But you do need some kind of IP that will model that memory or protocol for the formal tool. Some vendors can sell you a set of assertions that define a properly behaving AHB interface, for example. If you apply those assertions to the port on the DUT, then you don't need an actual simulation model. Others may provide a light-weight synthesizable model of the slave that doesn't do anything more than respond correctly to the master. The same applies to a memory.

    • Post Points: 20
  • Tue, Feb 11 2014 9:48 PM

    Re: initial statement issue in IFV Reply

    Thank you for telling me so much detail, I really enjoy and appreciate!

    • Post Points: 5
Page 1 of 1 (7 items)
Sort Posts:
Started by DouglasYaya at 07 Feb 2014 11:57 PM. Topic has 6 replies.