Are you working with power ports? If not, it seems like the library files need to be cleaned-up.
You will need library definitions for both golden and revised or else the set-up will be incomplete.
library cell and design code (e.g. verilog) need to match ports or else
the design code is syntatically incorrect. If the cell is a black box
then consider a stub model consisting of only the I/O.
the compare, library cells should have the same pin names to be EQ. I
searched the solutions and found a document which describes some ways of