I am Sivaramakrishna. My query is about the numerical/simulation errors in pnoise/pss analysis of VCO.
I am designing a (CMOS LC-) VCO and Interesting I am getting different phase-noise for the same circuit with with same settings, such as initial conditions, and integration methods(it was suggested that I need to use *trap* integration method in-order to get correct results).
Its varying around 1-to-2 dBc. I feel that this variation is significant as it is in log scale.
The only way I can, at least to the best of my knowledge, see if the numerical/simulation noise is playing any role. Could someone shed light on it.
Thanks and Regards