Home > Community > Forums > Digital Implementation > LVS verification for gds file from Cadence SOC Encounter

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 LVS verification for gds file from Cadence SOC Encounter 

Last post Tue, Jan 21 2014 1:02 AM by aflex. 1 replies.
Started by FMRLI 18 Jan 2014 04:23 AM. Topic has 1 replies and 4042 views
Page 1 of 1 (2 items)
Sort Posts:
  • Sat, Jan 18 2014 4:23 AM

    • FMRLI
    • Not Ranked
    • Joined on Fri, Feb 24 2012
    • Linköping,, Sweden
    • Posts 4
    • Points 65
    LVS verification for gds file from Cadence SOC Encounter Reply

     Hi,

    How to verify the LVS for gds file from Cadence SE. I have used 65nm STM standard cells for generating netlist file for layout and schematic design.  i am getting mismatch erros in Calibre LVS report  (INCORRECT). How to avoid bulk pins (vdds, gnds) in schematic, and missing instance (nsvtlp, psvtlp) cmos065.

     

    Thank you!!

    • Post Points: 20
  • Tue, Jan 21 2014 1:02 AM

    • aflex
    • Not Ranked
    • Joined on Thu, Nov 28 2013
    • Santa Ana, CA
    • Posts 10
    • Points 180
    Re: LVS verification for gds file from Cadence SOC Encounter Reply

    Try seperate analog vdd/gnd and digital vdd/gnd for crosstalk reduction from digital part. If if GND or VDD is on one metal use other metal for critical signal. 

    PCB Assembly Equipment

    PCB Layout Service 

    PCB Manufacturing & Designing
    • Post Points: 5
Page 1 of 1 (2 items)
Sort Posts:
Started by FMRLI at 18 Jan 2014 04:23 AM. Topic has 1 replies.