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# Algorithm used for implementation of Division

Last post Thu, Jan 9 2014 10:19 PM by S0MA. 2 replies.
 Started by S0MA 02 Jan 2014 11:00 PM. Topic has 2 replies and 4760 views
• #### Thu, Jan 2 2014 11:00 PM

• S0MA
• Joined on Thu, Jan 2 2014
• Bangalore, Karnataka
• Posts 3
• Points 30
Algorithm used for implementation of Division
 HiWhat is the default algorithm used for hardware implementation of division operation when synthesised using RC Compiler. Like the code below  begin quot[n:0] = divd/dvsr; remi = divd%dvsr;end
• Post Points: 20
• #### Tue, Jan 7 2014 12:14 PM

• Joined on Mon, Sep 8 2008
• Hamburg, Hamburg
• Posts 7
• Points 110
Re: Algorithm used for implementation of Division
 You want to know the internal behaviour of a commercial product. Cadence will never publish such a thing..Division in Verilog "/" is a fixed-point division, from which RTL Compiler generates division hardware by using synthetic operator DIV_UNS_OP or DIV_TC_OP. There are two other synthetic operators DIV_UNS_IEEE_OP and DIV_TC_IEEE_OP but I have not been able to force RTL Compiler to use them. Below this resolution nothing is visible to the user.Maybe this can give you a hint..
• Post Points: 20
• #### Thu, Jan 9 2014 10:19 PM

• S0MA
• Joined on Thu, Jan 2 2014
• Bangalore, Karnataka
• Posts 3
• Points 30
Re: Algorithm used for implementation of Division
 Sporadic,Thanks a lot for your response. I am just intersted to know what algorithm is used to synthesis the hardware like one among below or some other algorithm which is Cadence proprietary..?Restoring division, Non-restoring division, SRT division, Newton–Raphson division, Goldschmidt divisionThanks,Soma
• Post Points: 5
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 Started by S0MA at 02 Jan 2014 11:00 PM. Topic has 2 replies.