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 preserving a subdesign from optimization 

Last post Thu, Feb 27 2014 12:25 PM by grasshopper. 2 replies.
Started by P V S Shastry 30 Dec 2013 05:09 AM. Topic has 2 replies and 4858 views
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  • Mon, Dec 30 2013 5:09 AM

    preserving a subdesign from optimization Reply

    I wont to generate a fixed delay, for which I have used multiple NOT gates and instantiated in the top design.  While synthesizing, RTL compiler optimizes the gates added and put a direct net without delay.  How to get such fixed delays synthesized??

     

    • Post Points: 35
  • Fri, Jan 17 2014 2:07 AM

    • aflex
    • Not Ranked
    • Joined on Thu, Nov 28 2013
    • Santa Ana, CA
    • Posts 10
    • Points 180
    Re: preserving a subdesign from optimization Reply
    Speed-up IC Compiler placement by 1.5X. Also check the circuit congestion. This might help in fixing delays synthesized. 
    PCB Manufacturing & Designing
    • Post Points: 5
  • Thu, Feb 27 2014 12:25 PM

    • grasshopper
    • Top 25 Contributor
    • Joined on Thu, Jul 17 2008
    • Chelmsford, MA
    • Posts 242
    • Points 3,205
    Re: preserving a subdesign from optimization Reply

    I do not know what your HDL looks like but behavioral code for a chain of inverters would certainly be optimized. That is what synthesis tools are designed to do. You have several alternatives:

    (1) hand instantiate in HDL and preserve/dont_touch
    (2) use 'edit_netlist ...' commandsto create the buffer/delay cell chain

     gh-

    • Post Points: 5
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Started by P V S Shastry at 30 Dec 2013 05:09 AM. Topic has 2 replies.