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 Modify netlist of a block and resimulate (CDL.... CDF....) 

Last post Sat, Dec 28 2013 8:59 AM by Andrew Beckett. 1 replies.
Started by cozdag 28 Dec 2013 03:00 AM. Topic has 1 replies and 2317 views
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  • Sat, Dec 28 2013 3:00 AM

    • cozdag
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    • Joined on Sat, Dec 28 2013
    • Posts 2
    • Points 40
    Modify netlist of a block and resimulate (CDL.... CDF....) Reply

    Hello everyone,

    I am trying to pinpoint a layout error mechanism by modifying the av_extracred view netlist and resimulating the testbench. I have managed to create a manually written netlist as a spectre view before by following this tutorial:

    http://www.cadence.com/Community/blogs/rf/archive/2009/01/07/tip-of-the-week-how-to-simulate-a-subcircuit-netlist-with-spectre-in-ade.aspx

     But it was just a single resistors, and the library binding as I understand was by default analogLib, so it was relatively simple.

     This time, I want to modify a netlist with mosfets from TSMC and capacitors from analogLib (C extraction of a switch architecture I'm trying out). I got the netlist exported from CIW---> File ---> Export ---> CDL ---> choose the library/cell/view name and left all other options at default. Here is the output: http://www.pastebin.ca/2519207

    When I try to simulate this block using the technique in the tutorial I linked above, (CIW ---> CDF ---> Edit ---> ...) I get the following error:

    ================================ 

    Notice from spectre in `sw3_and_constantvgs_1_editable', during circuit

            read-in.

        "/home/caglarozdag/projects/TMSCOZDAG/cadence/sw3/sw3_and_constantvgs_1_editable"

            159: Use subckt `PD' as the master of `MI8|M0'

        "/home/caglarozdag/projects/TMSCOZDAG/cadence/sw3/sw3_and_constantvgs_1_editable"

            160: Use subckt `PD' as the master of `MM28'

        "/home/caglarozdag/projects/TMSCOZDAG/cadence/sw3/sw3_and_constantvgs_1_editable"

            161: Use subckt `PD' as the master of `MM27'

        "/home/caglarozdag/projects/TMSCOZDAG/cadence/sw3/sw3_and_constantvgs_1_editable"

            162: Use subckt `PD' as the master of `MI7|M0'

        "/home/caglarozdag/projects/TMSCOZDAG/cadence/sw3/sw3_and_constantvgs_1_editable"

            163: Use subckt `PD' as the master of `MM25'

            Further occurrences of this notice will be suppressed (except in log

            file).

    Error found by spectre in `sw3_and_constantvgs_1_editable', during circuit

            read-in.

        ERROR (SFE-400):

            "/home/caglarozdag/projects/TMSCOZDAG/cadence/sw3/sw3_and_constantvgs_1_editable"

            159: The instance `MI8|M0' does not have a valid master.

        ERROR (SFE-400):

            "/home/caglarozdag/projects/TMSCOZDAG/cadence/sw3/sw3_and_constantvgs_1_editable"

            160: The instance `MM28' does not have a valid master.

        ERROR (SFE-400):

            "/home/caglarozdag/projects/TMSCOZDAG/cadence/sw3/sw3_and_constantvgs_1_editable"

            161: The instance `MM27' does not have a valid master.

        ERROR (SFE-400):

            "/home/caglarozdag/projects/TMSCOZDAG/cadence/sw3/sw3_and_constantvgs_1_editable"

            162: The instance `MI7|M0' does not have a valid master.

    ...

    etc.

    ================================ 

     

    As far as I understand, capacitors in my netlists are taken from analogLib by default, so no problem there, just as it worked with my single resistor attempt. But the simulator is confused about how to handle the pchannel and nchannel mosfets.

     

    If my understanding of the problem is correct, my question is: How can I bind these mosfets to the tsmc mosfet models? Do I have to do this during my netlist export? Do I have to do this during my CDF edit?

     Thank you very much,

    -Caglar 

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    • Post Points: 20
  • Sat, Dec 28 2013 8:59 AM

    Re: Modify netlist of a block and resimulate (CDL.... CDF....) Reply

    Hi Caglar,

    First of all, I wouldn't use a CDL netlist to simulate with (unless it really was your only choice). CDL is a format that is SPICE-like, but is intended for physical verification. As a result, the model names are typically there to recognize a particular device, rather than matching the model name for simulation. Also, it won't have all the extracted parameters for each device, because LVS typically is not concerned with source/drain area & perimeter, LOD/STI/WPE parameters and so on. This is why you are getting lots of problems because the model names (subtypes in CDL) don't match the model names in your spectre models.

    So, what I would do is either get QRC to write out a SPICE file (rather than an extracted view), or I would produce a spectre netlist of the av_extracted view and take that as the source to modify. Whilst QRC does have the choice to output a spectre netlist directly, it does so by using an obsolete SPICE to spectre translator, and this flow is really not supported any more. Since many foundry PDKs only validate the extracted view flow, I would go for netlisting the av_extracted view.

    From IC616 ISR3 onwards, there is an option in ADE to include the subckt header for the top cellView - so if using that version you could open your extracted view, start ADE, and then turn on the top subckt option on the Setup->Environment form. Then do Simulation->Netlist->Create and then take your netlist for later modification.

    In earlier versions, use the hierarchy editor (or switch list in ADE) to include the av_extracted view in your normal testbench simulation. Then do a simulation->netlist->create and take the resulting netlist and chop out the subckt you are interested in.

    Hack this subckt to your heart's content, and then you can include it back in simulation using the approach suggested in Tawna's blog - the way you've been doing it so far.

    Kind Regards,

    Andrew.

    • Post Points: 5
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Started by cozdag at 28 Dec 2013 03:00 AM. Topic has 1 replies.