Rob, thanks for reply,
I read your other replies, and I think first problems with which Andrew also was helping out are solved. Now, its all about proper power net handling in an encounter cell in order to pass LVS and not having it complaining on power nets.
1) I am attaching the exported physical verilog file. Let me tell you something more, the standard cells have GND! and VDD! as a pins!
* I have no anything "GLOBAL" defined in standard cell CDL file
* I am not using any cdlGlobalMode setting
3) there is no I__13 in netlist, I__13 is an instance of "Layout" view, and there *is* of course I__13 in the layout. That specific error basically says that GND! net should not short to that instance at all. So its mad that GND! is shorted to GND! of that instance on the first place.
4) So, for example, when I was doing power routing in Encounter, I selected to connect global power VDD! to VDD! of each pin, and connect global power GND! to GND! of each pin. Otherwise it wouldnt connect, if I would for example "connect global VDD! to vdd of each pin" it would say something like "theres no vdd pin in a cell", again, because cells have VDD! and GND! pins as their power pins.
What really confusing is, as you know, it is wrong to short global to global etc, but thats the way kit comes! It has all cells with GND! and VDD! pins, and I am suspecting this is somehow makes LVS mad.
In other words, right now, LVS completes successfully, i.e. doesnt quit with error, but it just isnt happy with those power pins. I am not sure then now, what is the most proper way to handle those power connections?
5) Also, you know I actually found relatively similar post on this thread: http://www.cadence.com/community/forums/T/3023.aspx
But in my case situation is rather different, so, at this stage I just want to know what is the proper way to handle all those power related pins issue?