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 LVS versus physical Verilog from Encounter, Power Node Mismatch 

Last post Sun, Dec 22 2013 6:19 PM by Kabal. 5 replies.
Started by Kabal 19 Dec 2013 02:47 PM. Topic has 5 replies and 767 views
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  • Thu, Dec 19 2013 2:47 PM

    • Kabal
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    LVS versus physical Verilog from Encounter, Power Node Mismatch Reply

    OK, my battle over the LVS versus the physical Verilog file exported from Encounter continues. Finally, I think I kind of managed at least to get LVS working without quitting with error. i.e. it does run and completes successfully.

    However, right now I have another issue, which is basically netlist mismatch.  I am going to attach two files here, a picture with a snapshot of console window from which I export physical verilog from encounter, the LVS run options window where I show how I configure LVS before run. 

     Another file, is just LVS log output, where it tells what specifically does not match. Now let me discuss this, as you see it says something like: Layout net: GND! shorts to I__13/GND!

    I kind of don't get it. I mean GND! is global ground and VDD! is global power, they MUST "short" to GND! and VDD! of each cell of course. why would LVS complain?
     
    On the other hand, I know that globals cant be "shorted" to globals. But that is the way it was routed in encounter.
    As you know, in encounter for the power we usually put VDD! and for ground GND! and each GND! and VDD! of each cell connects to that global VDD!  and GND!.
     
    What is the proper way then to do it? 
     
    Or what is the proper way then to tell LVS that it is "OK" that those lines are shorting.
     
    (do not suggest something like cds_thru because I am doing LVS of layout versus the physical verilog file)
     
    Any ideas? 

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  • Thu, Dec 19 2013 2:48 PM

    • Kabal
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    Re: LVS versus physical Verilog from Encounter, Power Node Mismatch Reply
    and here is the LVS output file showing mismatches
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  • Fri, Dec 20 2013 12:50 AM

    Re: LVS versus physical Verilog from Encounter, Power Node Mismatch Reply

     Hi Kabal,

    Any chance you could go to customer support for this? My Assura LVS debugging skills are a bit rusty and I'm a bit pushed for time at the moment - so I don't have more than a few seconds to glance at this (also debugging just from the output log is always tricky - seeing the input data is usually quite important).

    Maybe somebody can help you on the forum, but by going to customer support you'll end up with an AE who focusses on Assura, plus will have dedicated time to look at the issue.

    Kind Regards,

    Andrew.

    • Post Points: 5
  • Fri, Dec 20 2013 4:43 AM

    • RobMan
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    Re: LVS versus physical Verilog from Encounter, Power Node Mismatch Reply

    Hi Kabal,

    Apologies. The thread got split and I responded another of your issues. So let's consider the VDD!/GND! issue.

    As you can probably ascertain this looks very much like GND!/VDD! connections are missing on the netlist side. This is invariably down to whether the pin connectivity and/or global declarations are correct.

    Does the 'physical' verilog connect GND! and VDD!
    Do you have *.GLOBAL in the cdl?
    Do you have any *.CDL_GLOBAL_MODE in the cdl?
    Do you have any cdlGlobalMode setting?

    Selecting a specific issue....
    Layout net: GND! shorts to I__13/GND!
    Can you identify the I__13 in the netlist?
    Can you identify why the GND! net connection does not make it up the hierarchy?

    It is puzzling that some cells are ok.
    Do you want to take this offline and perhaps share more of the rundir data?

    Rob.

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  • Sat, Dec 21 2013 4:47 PM

    • Kabal
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    Re: LVS versus physical Verilog from Encounter, Power Node Mismatch Reply

    Rob, thanks for reply,
    I read your other replies, and I think first problems with which Andrew also was helping out are solved. Now, its all about proper power net handling in an encounter cell in order to pass LVS and not having it complaining on power nets.

    1) I am attaching the exported physical verilog file. Let me tell you something more, the standard cells have GND! and VDD! as a pins!

     

    2)
     * I have no anything "GLOBAL" defined in standard cell CDL file

    * I am not using any cdlGlobalMode  setting 

    3) there is no  I__13 in netlist,  I__13 is an instance of "Layout" view, and there *is* of course  I__13 in the layout. That specific error basically says that GND! net should not short to that instance at all. So its mad that GND! is shorted to GND! of that instance on the first place. 

    4) So, for example, when I was doing power routing in Encounter, I selected to connect global power VDD! to VDD! of each pin, and connect global power GND! to GND! of each pin. Otherwise it wouldnt connect, if I would for example "connect global VDD! to vdd of each pin" it would say something like "theres no vdd pin in a cell", again, because cells have VDD! and GND! pins as their power pins.

     What really confusing is, as you know, it is wrong to short global to global etc, but thats the way kit comes! It has all cells with GND! and VDD! pins, and I am suspecting this is somehow makes LVS mad.

     In other words, right now, LVS completes successfully, i.e. doesnt quit with error, but it just isnt happy with those power pins. I am not sure then now, what is the most proper way to handle those power connections? 

     5) Also, you know I actually found relatively similar post on this thread:  http://www.cadence.com/community/forums/T/3023.aspx
    But in my case situation is rather different, so, at this stage I just want to know what is the proper way to handle all those power related pins issue? 

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  • Sun, Dec 22 2013 6:19 PM

    • Kabal
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    Re: LVS versus physical Verilog from Encounter, Power Node Mismatch Reply

    Alright, problem is nailed down. Here is how I solved it

    1) saveNetlist final.v -excludeLeafCell -includePowerGround

    2) Open the standard cell CDL file, and in the beginning of it put:
    .GLOBAL VDD! GND!

    3) In the LVS run window put in modified CDL file from (2) and exported from encounter verilog file from (1)

    4) Put a NO_SUBC_IN_GRLOGIC key in "switch keys" field.

     Thanks Rob, for giving me idea about that .GLOBAL thing. And to Alex Soyer helping along in another related thread., and to Andrew.

    And by the way, I was investigating that issue in parallel with official cadence support too, it was totally useless, the guy didnt even try to read in the log files I sent, rather than throwed at me some worked out example of some generic kit with LVS flow, which was not helpful in my case since IBM kit had different arrangment of setting files... 

    Anyhow, now I'm trying to figure out how to mix my imported design on schematic level with other analog custom schematics, but thats different case, I guess for now this LVS-related case is solved. 

    • Post Points: 5
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Started by Kabal at 19 Dec 2013 02:47 PM. Topic has 5 replies.