I have successfully imported the layout from Encounter, and solved out the residual DRC errors, however; I am not sure now how to do LVS.
Before I had some problems with import which were covered in another subforums here and topics but I solved them all, right now I want to concentrate just on a specific LVS on Encounter Imported Layout issue.
Here are my actions:
1) get the verilog design synthesized properly and routed without geometry/connectivity violations in Encounter [DONE]
2) Properly export it to GDS file [DONE]
3) do saveNetlist -phys -includePowerGround from the Encounter, it basically produces a Physical Verilog netlist, which includes cell description + Power pins. [DONE]
4) Go to Cadence Virtuoso, do CIW->Import->Verilog, there I point to the physical verilog netlist produced by Encounter and also point to the newly created library based on technology kit with imported proper metal layers.
5) then i start the process of importing scehmatics for CDL, I see that the cells are created one after another, and the main big schematics is created, where each module of the schematic is the standard library cell. However, when I click and get inside that cell I see only ports, and no transistors.
It might look OK, since afterall it has imported physical VERILOG netlist, not a transistor schematic.
But problem starts when I try to produce CDL netlist using the IBM provided Perl script for the LVS. The final output of that script is MY_INSTANCE_NAME.netlist.lvs
However, when I start now doing LVS on the corrected/DRCed Layout, I get errors like:
a) nMOS on layout is unbound to any schematic device
b) pMOS on Layout is unbound to any schematic device
c) subC on Layout unbound to schematic device
Error (c) is OK, I can fix it simbly by adding the substrate contact in the imported schematics.
(reason for that is that DRC does not pass without proper amount of substrate contacts on a layout, so in an imported layout I added them.. but then again, I added it also in the schematic, so error (c) was gone)
However, what really weird is: why do errors (a) and (b) exist?
From one side, I understand, it does not SEE the transistors because the cells imported from physical verilog dont have one (because verilog describes hardware flow not transistor interconnect)
But from another side, why would it even try to find transistors?
Why does not it treat my imported layout cells as a standalone modules with just ports, because that is what they are.
I even tried creating CDL netlist in "Digital" format from the imported schematics view, same thing.
Am I missing something trivial here?