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 Connect two nodes with different names 

Last post Thu, Jul 12 2007 3:30 AM by archive. 3 replies.
Started by archive 12 Jul 2007 03:30 AM. Topic has 3 replies and 3761 views
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  • Thu, Jul 12 2007 3:30 AM

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    Connect two nodes with different names Reply

    Hi All,

    I would like to short-circuit two nodes with different names.
    I have a 24 bits vector (let's say vect<0:23>) and would like to connect each of that node to either V3V or GND. I've used patch (from basic library) but it gives a warning (V3V collides with signal name vect<0> for instance). However it gives no fault during simulation.
    Is that good anyway and does it exist other connector? It should be LVS transparent in order to be used for tapeout.

    Thks in advance,
    Regards,

    Axel


    Originally posted in cdnusers.org by axp
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  • Mon, Jul 16 2007 12:43 PM

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    RE: Connect two nodes with different names Reply

    Hello, I have this same issue, and tried the same things as Axel did. Does anyone have any ideas?

    Thanks,
    S.M.


    Originally posted in cdnusers.org by mohta
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  • Tue, Jul 17 2007 12:30 AM

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    RE: Connect two nodes with different names Reply

    For this particular application I've finally found the way how to solve it out.
    Use a wire that you label with comma-separators. If the vector is specified vector<0:23>, the first signal name you write is the signal numbered 0 within the vector. (ex: signal0, signal1, signal2, signal3, ...)

    However, it's not yet a solution for the connection between two nodes with different names but it is somehow something that helped me.

    Regards
    Axel


    Originally posted in cdnusers.org by axp
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  • Tue, Jul 17 2007 12:57 AM

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    RE: Connect two nodes with different names Reply

    Axel,

    You should be able to use patch from basic (or Add->Patchcord in the schematic editor) to alias nets. The patch component can alias both single (scalar) nets and bus/bundle (vector) nets. The one thing you can't do is to alias two different terminals, two different global nets, or a terminal to a global net. For that, you can use the "cds_thru" component in basic. cds_thru ends up as something equivalent to a short in all the things it gets netlisted to - so for Verilog, it's a true through connection (because you can do that in Verilog); for spectre it's an "iprobe" (effectively a zero-volt source); for hspice it's a zero-volt source; for VirtuosoXL it will get shorted by VXL because it has lxRemoveDevice on it; for CDL it ends up as a small resistor (which generally can be shorted by the physical verification tool); and for Diva it ends up as a component that can be removed using removeDevice() in your LVS rules.

    That said, you should only use cds_thru for cases where patch can't be used. patch is a direct alias in the database, so that's better than introducing a real component in circuit simulators, say.

    Best Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett
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Started by archive at 12 Jul 2007 03:30 AM. Topic has 3 replies.