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 Verilog import to schematics problem 

Last post Thu, Nov 21 2013 9:27 PM by Kabal. 1 replies.
Started by Kabal 21 Nov 2013 04:59 PM. Topic has 1 replies and 761 views
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  • Thu, Nov 21 2013 4:59 PM

    • Kabal
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    • Joined on Thu, Sep 29 2011
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    Verilog import to schematics problem Reply

    Using Cadence version 6.15

    The final physical verilog was produced from Encounter after successful P&R using saveNetlist -phys final.v command, but when I am using Import Verilog I get the following error:

    ERROR (VERILOGIN-205): An internal memory error has occurred. Exiting.

    I did not find any descriptions in logs just that error and thats it. Any ideas why?  

    • Post Points: 5
  • Thu, Nov 21 2013 9:27 PM

    • Kabal
    • Top 50 Contributor
    • Joined on Thu, Sep 29 2011
    • NM, NM
    • Posts 179
    • Points 2,510
    Re: Verilog import to schematics problem Reply
    ok, redefining library, restarting tool helped.
    • Post Points: 5
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Started by Kabal at 21 Nov 2013 04:59 PM. Topic has 1 replies.