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 Force RTL compiler not to optimize certain part of the design 

Last post Wed, Nov 20 2013 3:03 PM by grasshopper. 1 replies.
Started by rexnyu 20 Nov 2013 01:55 PM. Topic has 1 replies and 5650 views
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  • Wed, Nov 20 2013 1:55 PM

    • rexnyu
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    • Joined on Tue, Mar 26 2013
    • Posts 15
    • Points 165
    Force RTL compiler not to optimize certain part of the design Reply

    Hi,

    I have a verilog design which has an input A which is 128-bit. I would like to use assign statement to let A equals to a fix value.

    But I don't want RTL compiler to optimize the logic associated with A, because I will give different values for A later in the spice level simulation. 

    Is there any synthesis constraints that can achieve this purpose? 

     

    Thank you very much! 

     

    • Post Points: 20
  • Wed, Nov 20 2013 3:03 PM

    • grasshopper
    • Top 25 Contributor
    • Joined on Thu, Jul 17 2008
    • Chelmsford, MA
    • Posts 241
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    Re: Force RTL compiler not to optimize certain part of the design Reply

     try

    set_attr preserve true <net tied to constant>

     gh-

    • Post Points: 5
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Started by rexnyu at 20 Nov 2013 01:55 PM. Topic has 1 replies.